4acdc67485
This uses an reorder queue but doesn't check to ensure that the data it fetches from the queue is actually in the queue before using it. It seems that during correct operation this never breaks, but I'm trying to get the backup memory port working again and this assertion fails with it enabled (without the assertion the core just gets a bogus data beat dies). Closes #16 |
||
|---|---|---|
| .. | ||
| project | ||
| src/main/scala | ||
| .gitignore | ||
| build.sbt | ||
| LICENSE | ||
| README.md | ||
Uncore Library
This is the repository for uncore components assosciated with Rocket chip project. To uses these modules, include this repo as a git submodule within the your chip repository and add it as a project in your chip's build.scala. These components are only dependent on the ucb-bar/chisel repo, i.e.
lazy val uncore = project.dependsOn(chisel)
ScalaDoc for the uncore library is available here and an overview of the TileLink Protocol is available here, with associated CoherencePolicy documentation here.