1ac9f59b31
Right now there's no way to ensure that SCR addresses don't conflict within RocketChip. Since upstream only has one of them this isn't a big deal, but we want to add a whole bunch more to control all the IP on Hurricane. This patch adds some Scala code to allocate registers inside the SCR file, ensure they don't conflict, to provide names for SCRs, attach registers to the SCR file, and generate a C header file that contains the addresses of every SCR on a chip. With this patch we'll be able to get rid of that constant in the testbench. This also allows us to kill one of the Raven diffs, which is does pretty much the same thing (just in a second SCR file, and hacked in). |
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| README.md | ||
Uncore Library
This is the repository for uncore components assosciated with Rocket chip project. To uses these modules, include this repo as a git submodule within the your chip repository and add it as a project in your chip's build.scala. These components are only dependent on the ucb-bar/chisel repo, i.e.
lazy val uncore = project.dependsOn(chisel)
ScalaDoc for the uncore library is available here and an overview of the TileLink Protocol is available here, with associated CoherencePolicy documentation here.