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Commit Graph

145 Commits

Author SHA1 Message Date
Henry Cook
e8b20f3d38 clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant 2013-04-25 17:41:04 -07:00
Andrew Waterman
ae7720e284 guarantee LR/SC forward progress
the mechanism is to block new probes for several cycles after a successful LR.

this also cleans up the MSHR <-> ProbeUnit interface slightly.
2013-04-07 19:27:21 -07:00
Andrew Waterman
e74e032c87 simplify MSHR memory response logic 2013-04-06 01:03:37 -07:00
Andrew Waterman
1abb9277db fix LR/SC atomicity violation
note, it's still not starvation-free.
2013-04-05 19:13:38 -07:00
Andrew Waterman
8cbdeb2abf add LR/SC support 2013-04-04 17:07:09 -07:00
Henry Cook
f8aebcbf8c fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match 2013-04-04 15:50:29 -07:00
Henry Cook
95f0a688e9 Merge branch 'release-xacts'
Conflicts:
	src/htif.scala
	src/icache.scala
	src/nbdcache.scala
	src/tile.scala
2013-03-20 17:37:50 -07:00
Henry Cook
273bd34091 Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants. 2013-03-20 15:53:36 -07:00
Andrew Waterman
ea9d0b771e remove aborts; simplify probes 2013-03-19 15:29:40 -07:00
Henry Cook
e0361840bd writebacks on release network pass asm tests and bmarks 2013-02-28 18:11:40 -08:00
Andrew Waterman
35349d227f update to new Mem style 2013-02-20 16:09:46 -08:00
Andrew Waterman
1fbc20450e don't allow simultaneous reads and writes to the tag ram 2013-01-24 17:55:00 -08:00
Andrew Waterman
37ee843b2c don't use reset combinationally 2013-01-24 17:55:00 -08:00
Andrew Waterman
bb6fbddf1f don't probe the mshr file to inquire about refills 2013-01-24 17:54:59 -08:00
Rimas Avizienis
63060bc0a8 minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc) 2013-01-23 19:27:53 -08:00
Henry Cook
6b00e7ff74 New TileLink bundle names 2013-01-21 17:18:23 -08:00
Henry Cook
a2fa3fd04d Refactored packet headers/payloads 2013-01-15 15:50:37 -08:00
Henry Cook
e1225c5114 standardize IO naming convention 2013-01-07 13:41:36 -08:00
Henry Cook
261e14f831 Refactored uncore conf 2013-01-07 13:41:36 -08:00
Andrew Waterman
f5c53ce35d add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
2012-12-11 15:58:53 -08:00
Andrew Waterman
3f59e439ef fix d$ tag raw hazard 2012-12-07 15:14:20 -08:00
Andrew Waterman
4dda38204f fix d$ reset bug 2012-12-06 03:13:22 -08:00
Andrew Waterman
290d3d226c fix AMO and store bypass bugs
thanks, torture tester
2012-12-06 02:07:52 -08:00
Andrew Waterman
4608660f6e torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
2012-12-04 05:57:53 -08:00
Andrew Waterman
90cae54ac4 fix D$ read/write concurrency bug 2012-11-27 02:42:27 -08:00
Andrew Waterman
608f65e716 don't wastefully read 2x the bits from D$ RAMs 2012-11-26 20:34:30 -08:00
Andrew Waterman
8a6ff5f9aa fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
2012-11-25 19:46:48 -08:00
Andrew Waterman
de2f28193a get rid of more global constants 2012-11-25 04:24:25 -08:00
Andrew Waterman
c036cdc1ea add option for 2-cycle load-use delay 2012-11-24 22:01:08 -08:00
Andrew Waterman
2b26082132 use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
2012-11-20 04:09:26 -08:00
Andrew Waterman
30038bda8a bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
2012-11-20 01:33:32 -08:00
Yunsup Lee
395e4e3dd6 andrew'x fix for D$ corner case in writeback->abort->probe 2012-11-18 03:11:06 -08:00
Yunsup Lee
81d711e892 fix D$ bug; now D$ doesn't respond to prefetches 2012-11-17 20:06:13 -08:00
Andrew Waterman
29bc361d6c remove global constants; disentangle hwacha a bit 2012-11-17 17:24:08 -08:00
Andrew Waterman
e68b039133 fix misc. D$ control bugs 2012-11-17 06:47:27 -08:00
Andrew Waterman
dad7b71062 provide cmd/addr with cache response 2012-11-16 21:26:12 -08:00
Andrew Waterman
cb8ac73045 provide store data with cache response 2012-11-16 21:15:13 -08:00
Andrew Waterman
9e010beffe fix D$ refill bug 2012-11-16 21:05:29 -08:00
Andrew Waterman
8dce89703a new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
2012-11-16 02:39:33 -08:00
Andrew Waterman
6d10115b19 fix D$ tag width 2012-11-15 16:46:39 -08:00
Yunsup Lee
9a02298f6f andrew's fix for tlb lockup 2012-11-06 23:52:58 -08:00
Andrew Waterman
4d1ca8ba3a remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
2012-11-06 08:13:44 -08:00
Andrew Waterman
c5b93798fb factor out more global constants 2012-11-05 23:52:32 -08:00
Henry Cook
88ac5af181 Merged consts-as-traits 2012-10-16 16:32:35 -07:00
Andrew Waterman
fc648d13a1 remove old Mux1H; add implicit conversions 2012-10-16 02:24:37 -07:00
Henry Cook
8970b635b2 improvements to implicit RocketConfiguration parameter 2012-10-15 16:29:49 -07:00
Henry Cook
9025d0610c first pass at configuration object passed as implicit parameter 2012-10-07 22:37:29 -07:00
Andrew Waterman
ed8cc4a1cf eliminate D$ probe->WB critical path 2012-10-04 09:05:14 -07:00
Huy Vo
e909093f37 factoring out uncore into separate uncore repo 2012-10-01 16:08:41 -07:00
Henry Cook
b9a9664de5 uncore and rocket changes for new xact types 2012-10-01 10:47:36 -07:00