riscv/rocket-chip
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82 Commits

Author SHA1 Message Date
Wesley W. Terpstra
93b2fa197e Artefact output (#545) 
* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
 2017-02-02 19:24:55 -08:00
GuzTech
8157cf1ede Perform integer division when parsing rocketchip.DefaultConfig.conf (#493) 2017-01-13 16:40:02 -08:00
Colin Schmidt
f19d504c88 Use % in makefrag-verilog to prevent double firrtl execution (#452) 
* Use % in makefrag-verilog to prevent double firrtl execution
 2016-11-25 01:50:01 -08:00
Andrew Waterman
f3c726033a Make all Chisel invocations depend on FIRRTL_JAR 2016-10-28 11:56:05 -07:00
Jack Koenig
288d7169ae Bump firrtl and update vsim Makefrag-verilog (#409) 2016-10-23 23:07:47 -07:00
Andrew Waterman
7f429e8799 Simplify AsyncResetReg 
No need for AsyncSetReg, as AsyncResetReg can be used exclusively with
inverted inputs.
 2016-10-08 21:29:40 -07:00
mwachs5
77a0f76289 Cleanup jtag dtm (#342) 
* debug: Clean up Debug TransportModule synchronizer

With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.

I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
 2016-09-26 11:10:27 -07:00
Henry Cook
1e54820f8c Merge remote-tracking branch 'origin/master' into unittest-config 2016-09-22 16:03:51 -07:00
Henry Cook
411ee378de Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. 2016-09-22 15:59:29 -07:00
Howard Mao
cd96a66ba6 replace verilog clock divider with one written in Chisel 2016-09-22 11:32:29 -07:00
Andrew Waterman
8e63f4a1a5 Remove ClockToSignal and vice-versa 
Clock.asUInt and Bool.asClock now suffice.
 2016-09-21 16:17:14 -07:00
Henry Cook
2961d92244 [testharness] vsim makefrag cleanup 2016-09-19 15:14:45 -07:00
Henry Cook
ddcf1b4099 Use PROJECT rather than MODEL in name of binary and generated src files. 2016-09-19 13:23:17 -07:00
Richard Xia
63f13ae7ce Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor 2016-09-16 17:10:52 -07:00
mwachs5
a031686763 util: Do BlackBox Async Set/Reset Registers more properly (#305) 
* util: Do Set/Reset Async Registers more properly

The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.

This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).

* Tabs, not spaces, in Makefiles

* util: Fix typos in Async BB Reg Comments
 2016-09-16 13:50:09 -07:00
Henry Cook
9e2b0aad65 Revert "allow MODEL to be something other than TestHarness" 
This reverts commit bf253aaa97.
 2016-09-15 11:53:05 -07:00
Howard Mao
bf253aaa97 allow MODEL to be something other than TestHarness 2016-09-14 20:51:56 -07:00
Howard Mao
8550582f84 remove redundant verilator rule 2016-09-14 20:31:17 -07:00
jackkoenig
a304695ffd Add firrtl and verilog Makefile targets to vsim 2016-09-14 20:29:59 -07:00
Megan Wachs
1308680f75 Add some async/clock utilities 2016-09-14 16:30:59 -07:00
Andrew Waterman
2572cd3f7c Add missing dependency 2016-09-14 11:50:28 -07:00
Megan Wachs
fda4c2bd76 Add a way to create Async Reset Registers and a way to easily access them with TL2 2016-09-08 20:02:07 -07:00
Ben Keller
6be569be9f Turn on the inferRW Firrtl pass 
Without this, all of the memories wind up as two-ported.
 2016-09-07 15:27:26 -07:00
Colin Schmidt
92718e4b61 fix null statement in vsli_mem_gen ala firrtl#264 (#252) 2016-09-07 11:04:36 -07:00
Megan Wachs
e95fe646a3 mem_gen failure doesn't create the target 2016-09-06 16:29:29 -07:00
Megan Wachs
48098f5e2d Bump FIRRTL to instantiate Sequential Memory Macros 2016-09-06 14:48:28 -07:00
Megan Wachs
1fec9807f6 allow override of vlsi_mem_gen script 2016-09-06 14:44:12 -07:00
Yunsup Lee
4a7972be31 connect testharness components via member functions (#236) 
to prevent code duplication for new testbenches
 2016-09-01 18:38:39 -07:00
Howard Mao
08089f695d allow configuration to be in separate project from test harness 2016-09-01 10:28:07 -07:00
Howard Mao
a19bd6de96 Get in line with FIRRTL randomization flag changes (#231) 2016-08-29 12:29:01 -07:00
Henry Cook
93c801f598 Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227) 2016-08-25 17:26:28 -07:00
Ben Keller
4f388add67 More accurate conditional include of generated .d make fragment (#222) 2016-08-25 14:42:04 -07:00
Scott Johnson
96e2cefb34 Merge branch 'master' into HEAD 2016-08-22 11:37:30 -07:00
Scott Johnson
2d12f6689c make CLOCK_PERIOD actually be the clock period, instead of half of the clock period 2016-08-19 16:55:57 -07:00
Megan Wachs
dd4a50c452 Add JTAG DTM and test support in simulation 
Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box
 2016-08-19 16:08:17 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel 
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
 2016-08-15 23:27:27 -07:00
Howard Mao
dd1fed41b6 generate BootROM contents from assembly code 2016-08-05 16:39:21 -07:00
Andrew Waterman
32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al 2016-07-07 21:23:49 -07:00
Howard Mao
39ec927a3f replace complicated pattern substitutions with automatic variable 2016-06-28 18:30:11 -07:00
Howard Mao
a39a0c0ec4 .prm is output of chisel stage, not firrtl stage 2016-06-28 17:34:37 -07:00
Andrew Waterman
87a4858aa6 Exit from testbench, not C code 
Otherwise, we don't get coverage data from the simulator.
 2016-06-23 20:54:07 -07:00
Andrew Waterman
568bfa6c50 Purge legacy HTIF things 
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
 2016-06-23 13:23:57 -07:00
Howard Mao
daa0f3038f invoke firrtl jar directly in order to control heap memory usage 2016-06-20 13:02:31 -07:00
Palmer Dabbelt
e6c4372332 Fix "make run-asm-tests" for Chisel 3 
This was just a missing Makefrag-verilog dependency (the .d file).
 2016-06-06 21:36:55 -07:00
Wesley W. Terpstra
da566e7d6a build: use local sbt when building firrtl 2016-05-25 11:48:03 -07:00
Andrew Waterman
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Howard Mao
18ffe7b1ec don't use +verbose in vsim .run rule 2016-05-04 23:01:14 -07:00
Andrew Waterman
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
Andrew Waterman
1f211b37df WIP on new memory map 2016-04-27 14:57:54 -07:00
Andrew Waterman
46d7dceb1e Disable printf/assert during reset 2016-04-01 18:18:08 -07:00