riscv/rocket-chip
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generate BootROM contents from assembly code

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This commit is contained in:
Howard Mao
2016-08-05 11:07:42 -07:00
parent dab96096b4
commit dd1fed41b6
11 changed files with 49 additions and 19 deletions
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vsim/Makefrag-verilog
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@ -16,7 +16,7 @@ else
# files.
.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs)
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(notdir $*) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem"
mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir