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rocket-chip/vsim
Andrew Waterman 568bfa6c50 Purge legacy HTIF things
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
..
.gitignore update for rocket-chip release 2014-08-31 20:26:55 -07:00
Makefile Add blocking D$ 2016-05-25 11:09:50 -07:00
Makefrag Purge legacy HTIF things 2016-06-23 13:23:57 -07:00
Makefrag-verilog invoke firrtl jar directly in order to control heap memory usage 2016-06-20 13:02:31 -07:00
vlsi_mem_gen Massive update containing several months of changes from the now-defunct private chip repo. 2015-07-02 14:43:30 -07:00