Andrew Waterman
5fd5b58743
Remove stats CSR
2016-04-26 15:31:32 -07:00
Andrew Waterman
d93677a343
Support larger cache sets when not using VM
2016-04-26 15:31:32 -07:00
Yunsup Lee
5dbf9640e2
Use TLB flush signal to I$ explicitly
2016-04-22 15:41:31 -07:00
Andrew Waterman
84fd45fd77
Pass TLB flush signal to I$ explicitly
2016-04-22 15:20:17 -07:00
Howard Mao
b7527268bb
use address map instead of MMIOBase to find size of memory
2016-04-21 18:44:39 -07:00
Christopher Celio
2d6f35525e
Added Field[Int] to SFMALatency/DFMALatency params
2016-04-06 14:50:57 -07:00
Andrew Waterman
51e0870e23
Separate I$ and D$ interface signals that span clock cycles
...
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
2016-04-01 19:30:39 -07:00
Andrew Waterman
dc662f28a0
Specify width on s1_pc to avoid width inference problem
2016-04-01 17:28:42 -07:00
Andrew Waterman
72f7f71eb5
No need to allow finishes to be sent in s_refill_resp state
...
This is a hold-over from when writebacks needed finish messages.
2016-04-01 16:19:57 -07:00
Henry Cook
78bc18736e
LRSC startvation fix: HellaCache generates its own Finish messages again.
2016-04-01 16:04:25 -07:00
Andrew Waterman
37b9051762
No need to validate npc if BTB is disabled
2016-04-01 15:54:57 -07:00
Andrew Waterman
4480d1e817
Don't compile BTB when nEntries=0
2016-04-01 15:14:45 -07:00
Andrew Waterman
d406dc1231
Remove vestigial BTB enable option
2016-04-01 15:14:34 -07:00
Henry Cook
54dd82ff76
bugfix for WB data buffer
2016-03-31 17:53:49 -07:00
Christopher Celio
1792d01ce1
fix leaky assert in nbdcache
...
Squash of #33 .
2016-03-31 15:56:14 -07:00
Andrew Waterman
adb7eacf6e
Fix Chisel3 build for XLen=32
2016-03-30 22:48:51 -07:00
Andrew Waterman
70664bbca0
Fix Chisel3 build for UseVM=false
2016-03-30 22:48:31 -07:00
Andrew Waterman
8ad8e8a691
Add partial Sv48/Sv57 support
...
Right now, we don't support Sv39 and Sv48 at the same time, which needs
to change.
2016-03-30 11:02:22 -07:00
Andrew Waterman
e652821962
Use correct kind of TileLink arbiter
...
It was "correct" before, but broke Chisel3 build.
2016-03-28 22:53:47 -07:00
Andrew Waterman
5ce3527b88
Merge pull request #32 from ucb-bar/pr-btb-masking
...
separate btb response mask from the frontend mask
2016-03-26 18:15:14 -07:00
Christopher Celio
f526d380fd
separate btb response mask from the frontend mask
...
It is now the job of the pipeline to monitor the frontend's valid mask (of
instructions) and the BTB's suggested valid mask (based on the prediction it
makes). Some processors may want to ignore or override the BTB's prediction and
thus can supply their own instruction mask.
2016-03-26 05:37:26 -07:00
Andrew Waterman
ed280fb3de
Remove empty when statement (???)
2016-03-25 15:52:18 -07:00
Andrew Waterman
1ae6d09751
Slightly ameliorate D$->I$ critical path via scoreboard
2016-03-25 15:29:32 -07:00
Andrew Waterman
a4685a073f
Don't instantiate PTW when UseVM=false
2016-03-25 14:17:25 -07:00
Andrew Waterman
27b3cca046
Discover D$, PTW port counts dynamically
...
This is a generator, after all...
2016-03-25 14:16:56 -07:00
Andrew Waterman
8d1ba4d1ec
Remove hard-coded XLEN values from D$
2016-03-24 14:52:12 -07:00
Andrew Waterman
7ae44d4905
Add RV32 support
2016-03-10 17:32:00 -08:00
Andrew Waterman
82c595d11a
Fix no-FPU elaboration of CSR file
2016-03-10 17:30:56 -08:00
Andrew Waterman
bc15e8649e
WIP on priv spec v1.9
2016-03-02 23:29:58 -08:00
Yunsup Lee
15ac4d317f
RoCC PTW refactoring
2016-02-25 17:15:38 -08:00
Christopher Celio
b96343a4e5
[btb] fix mix type error for fetch-width > 1
...
closes #24
2016-02-08 17:41:38 -08:00
Christopher Celio
31dd311aff
[fpu] fix rounding mode bug in fdivfsqrt
2016-02-08 17:38:31 -08:00
Howard Mao
5abfd1a4ab
make sure to check for region violations in DMA frontend
2016-02-03 15:40:44 -08:00
Howard Mao
78579672d3
make mtvec configurable and writeable
2016-01-29 14:51:56 -08:00
Howard Mao
7937fbf074
fix number of IOMSHRs at 1
2016-01-29 14:51:56 -08:00
Howard Mao
305185c034
send DMA requests through MMIO and get responses through CSRs
2016-01-29 14:51:56 -08:00
Andrew Waterman
58fcc6b7c6
Get rid of useless mux
2016-01-28 11:44:59 -08:00
Howard Mao
d170fcd913
DecoupledHelper is now imported from junctions
2016-01-21 15:38:43 -08:00
Andrew Waterman
52d6b0b1a5
Improve ALU QoR
...
Rejigger muxes; share XOR gates between ADD/SUB, XOR, and BEQ.
2016-01-20 17:42:31 -08:00
Howard Mao
77e068c153
fix Chisel3 compat issue in SimpleHellaCacheIF
2016-01-14 22:42:44 -08:00
Howard Mao
120361226d
fix more Chisel3 deprecations
2016-01-14 14:46:31 -08:00
Howard Mao
d51c127646
fix deprecation warnings in rocket.scala
2016-01-13 22:08:06 -08:00
Andrew Waterman
ae98af7077
don't mix SInt/UInt
2016-01-12 16:27:36 -08:00
Andrew Waterman
00d17abd78
Don't ignore data value when writing MIPI
2016-01-12 16:23:06 -08:00
Andrew Waterman
7bf503a275
Remove four integer/FP converters
2016-01-12 16:06:23 -08:00
Andrew Waterman
31d537c405
Add missing cloneType
2016-01-12 15:45:11 -08:00
Howard Mao
13ce91e453
fix Chisel3 compat warnings in ICache and FPU
2016-01-12 12:43:48 -08:00
Howard Mao
05b359d357
support streaming DMA in DMA frontend
2016-01-06 18:17:41 -08:00
Howard Mao
304d8b814a
Implement client-side DMA controller
2015-12-16 21:24:24 -08:00
Albert Magyar
01a3447989
Remove duplicate PseudoLRU class from rocket TLB
2015-12-16 16:12:47 -08:00
Howard Mao
7690de07e1
allow icache to configure which side of the way mux gets buffered
2015-12-02 17:17:49 -08:00
Howard Mao
369ee74a2c
change names of RoCC tilelink interfaces to be more sensible
2015-12-02 16:28:23 -08:00
Howard Mao
73b0263663
disconnect fpu port if no fpu-using RoCC accelerators
2015-12-01 20:41:58 -08:00
Howard Mao
dcca0b1d86
fix up FPU connection
2015-12-01 18:14:58 -08:00
Howard Mao
08f77ca90d
Merge branch 'master' into rocc-fpu-port
2015-12-01 18:00:28 -08:00
Howard Mao
e76dfa55f7
change the way rocc is parameterized
2015-12-01 17:54:56 -08:00
Howard Mao
4833d41dbc
make the connection of FPU ports optional per accelerator
2015-12-01 16:48:05 -08:00
Howard Mao
0b15b19381
add arbiter for FPU
2015-12-01 10:22:31 -08:00
Howard Mao
1db2da00f3
Merge branch 'master' into rocc-fpu-port
2015-11-30 19:18:58 -08:00
Howard Mao
e80340198a
use implicit parameters for ALU
2015-11-30 17:35:33 -08:00
Howard Mao
9256239206
implement support for multiple RoCC accelerators
2015-11-26 12:46:01 -08:00
Howard Mao
58b0a86834
some modifications to AccumulatorExample
2015-11-26 08:48:19 -08:00
Andrew Waterman
e203b8b378
Make ALU generic for zscale
2015-11-24 19:17:07 -08:00
Andrew Waterman
5294e94794
Remove CSR back pressure ability
...
We were using it for IPIs, but no longer need it.
2015-11-24 18:28:14 -08:00
Andrew Waterman
4616db4695
Make RegFile/ImmGen usable by zscale
2015-11-24 18:27:07 -08:00
Andrew Waterman
6d1bf5c014
Use generic LoadGen/StoreGen
2015-11-24 18:13:33 -08:00
Sagar Karandikar
65632c875a
Merge branch 'master' into rocc-fpu-port
2015-11-21 02:24:38 -08:00
Howard Mao
b0a06a77db
fix a few Chisel3 compat issues
2015-11-20 13:33:15 -08:00
Yunsup Lee
94d2dd3053
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-11-16 23:29:25 -08:00
Andrew Waterman
0f092b9b59
Remove IPI network
...
This is now provided via MMIO.
2015-11-16 21:51:43 -08:00
Yunsup Lee
5e2698adbc
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-11-14 16:44:55 -08:00
Yunsup Lee
213c1a4c81
fix fdiv/fsqrt control bug in fpu
2015-11-14 16:43:15 -08:00
Yunsup Lee
4dd097d156
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-11-14 14:52:13 -08:00
Yunsup Lee
3c3c946755
move to new version of hardfloat
2015-11-14 14:49:17 -08:00
Yunsup Lee
608e4b2851
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-11-12 20:44:25 -08:00
Howard Mao
19daee10f0
use default constructors for IOMSHR acquire construction
2015-11-12 15:54:05 -08:00
jackkoenig
1e259a55da
Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later
2015-11-08 21:16:31 -08:00
Yunsup Lee
df5daaa72e
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-11-06 23:57:42 -08:00
Andrew Waterman
2f515b2af6
Reduce critical path for fdiv valid signal
2015-11-06 23:28:31 -08:00
Colin Schmidt
86d67051b2
Merge commit 'e31be75' into rocc-fpu-port
2015-10-26 16:29:51 -07:00
Yunsup Lee
c7235fecb5
further state optimization in CSRfile when not UseVM
2015-10-25 10:23:46 -07:00
Colin Schmidt
652fb393a3
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-10-22 16:38:28 -07:00
Jim Lawson
0c587704a7
Add ability to generate libraryDependency on cde.
2015-10-22 11:37:20 -07:00
Henry Cook
4f8468b60f
depend on external cde library
2015-10-21 18:19:23 -07:00
Colin Schmidt
942f6a7d7f
Merge commit 'd1eae61970f864afe4fde8ca7f75380c70c4658f' into rocc-fpu-port
2015-10-21 17:18:20 -07:00
Colin Schmidt
97f29b1618
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-10-21 11:33:42 -07:00
Howard Mao
0b7c828b5d
go back to using standard LockingArbiter
2015-10-21 09:15:51 -07:00
Howard Mao
c68d9f8137
make ProbeUnit state machine easier to understand
2015-10-20 23:25:23 -07:00
Henry Cook
1a1185be3f
Vectorize ROCC and Tile memory interfaces
2015-10-20 15:02:24 -07:00
Colin Schmidt
2cee8c8bec
Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port
2015-10-18 13:09:17 -07:00
Henry Cook
6f8997bee9
Minor refactor of StoreGen/AMOALU.
2015-10-16 19:12:46 -07:00
Henry Cook
1441590c3b
add enabled field to BTBParameters
2015-10-16 19:12:39 -07:00
Henry Cook
969ecaecf8
pass parameters to BuildRoCC
2015-10-14 14:16:47 -07:00
Henry Cook
68cb54bc68
refactor tilelink params
2015-10-14 12:14:36 -07:00
Henry Cook
4508666d96
log2ceil
2015-10-06 18:22:47 -07:00
Henry Cook
8173695800
added HasAddrMapParameters
2015-10-06 18:22:40 -07:00
Henry Cook
84576650b5
Removed all traces of params
2015-10-05 21:48:05 -07:00
Henry Cook
69a4dd0a79
refactor NASTI to not use param
2015-10-02 14:20:47 -07:00
Howard Mao
19656e4abe
make sure to generate release from clean coh state on probe miss
2015-09-30 16:58:18 -07:00
Andrew Waterman
833909a2b5
Chisel3 compatibility fixes
2015-09-30 14:36:26 -07:00
