Wesley W. Terpstra
7a24527448
ahb: make MMIO channels specifiy bus type (we will have more than one bridge)
2016-06-06 21:35:30 -07:00
Wesley W. Terpstra
f3a557b67b
ahb: AHB parameters should be site specific
...
Conflicts:
src/main/scala/Configs.scala
2016-06-06 21:35:24 -07:00
Andrew Waterman
4f2e2480a8
When exceptions occur in D-mode, set pc=0x808, not 0x800
...
Closes #43
2016-06-06 20:57:22 -07:00
Howard Mao
172c4f25f4
bump groundtest and uncore
2016-06-06 17:45:30 -07:00
Howard Mao
f44778fa56
make sure Cached generator comparison truncates to correct size
2016-06-06 17:45:04 -07:00
Howard Mao
ff2937a788
include the unmatched field in CDEMatchError
2016-06-06 11:23:20 -07:00
Howard Mao
022503748e
make Memtest generators more configurable
2016-06-06 09:44:09 -07:00
Howard Mao
2163ebfca3
use a generic Nasti memory driver for unit tests
2016-06-06 09:43:39 -07:00
Howard Mao
2d66ac93d3
make sure HastiRAM cuts off the correct number of bits for word address
2016-06-06 09:26:51 -07:00
Andrew Waterman
d24c87f8ba
Update PLIC/PRCI address map ( #124 )
2016-06-06 04:51:55 -07:00
Andrew Waterman
dd85f2410f
Avoid need for cloneType
2016-06-05 23:47:56 -07:00
Andrew Waterman
631e3e2dd9
Make PRCI a singleton, not per-tile
...
Some stuff is densely packed in the address space (e.g. IPI regs),
so needs to be on the same TileLink slave port
2016-06-05 23:06:21 -07:00
Andrew Waterman
be7500e4a9
Update PLIC addr map
2016-06-05 23:04:51 -07:00
Megan Wachs
b832689642
Correct Debug ROM contents
2016-06-05 19:35:25 -07:00
Megan Wachs
605fb5b92f
[debug]: fix issue with subword select logic
2016-06-05 19:31:07 -07:00
Megan Wachs
3e8322816b
Correct DMINFO Fields
2016-06-05 19:29:50 -07:00
Megan Wachs
7e550ab07c
[debug] rocket: fix for issue 121, correct debug ROM and stall logic
2016-06-05 19:29:44 -07:00
Andrew Waterman
ece3ab9c3d
Refactor AddrMap and its usage ( #122 )
2016-06-03 17:29:05 -07:00
Andrew Waterman
3b0c1ed0c3
Cope with changes to AddrMap
2016-06-03 13:50:29 -07:00
Andrew Waterman
cf8be98b2b
Cope with changes to AddrMap
2016-06-03 13:48:43 -07:00
Andrew Waterman
2e88ffc364
Cope with changes to AddrMap
2016-06-03 13:48:09 -07:00
Andrew Waterman
28161cab45
Merge AddrHashMap and AddrMap
2016-06-03 13:46:53 -07:00
Andrew Waterman
f1745bf142
Allow PLIC nPriorities=0 (priority fixed at 1)
2016-06-02 13:48:29 -07:00
Andrew Waterman
b7ca2145b3
Fix PLIC control bug when !grant.ready
2016-06-02 13:47:59 -07:00
Andrew Waterman
c8338ad809
Instantiate Debug Module ( #119 )
2016-06-02 10:53:41 -07:00
Andrew Waterman
0866b4c045
Can't assign to Vec literals
2016-06-01 23:36:34 -07:00
Andrew Waterman
20e1de08da
Avoid chisel2 pitfall
...
This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3. D'oh.
2016-06-01 23:35:49 -07:00
Andrew Waterman
5629fb62bf
Avoid bitwise sub-assignment
2016-06-01 21:59:02 -07:00
Andrew Waterman
9518b3d589
Fix arithmetic in ROM row count
2016-06-01 21:59:02 -07:00
Andrew Waterman
8e80d1ec80
Avoid floating-point arithmetic where integers suffice
2016-06-01 21:59:02 -07:00
Andrew Waterman
13386af1d1
Get rid of unused implicit conversion
2016-06-01 19:30:41 -07:00
Andrew Waterman
9949347569
First stab at debug interrupts
2016-06-01 16:57:10 -07:00
Wesley W. Terpstra
11b3cee07a
Ahb tweaks ( #50 )
...
* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully
I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.
* ahb: optionally disable atomics => optimize to nothing
Trust the compiler the compiler to optimize away unused logic.
2016-06-01 16:42:39 -07:00
Wesley W. Terpstra
695be2f0ae
hasti: work-around unsupported 0-width signals
2016-06-01 16:38:49 -07:00
mwachs5
740a6073f6
Add Debug Module ( #49 )
...
* Add Debug Module
* [debug] Remove unit tests, update System Bus register addresses, parameterize nComponents
* [debug] Update Debug ROM contents to match updated addresses
2016-06-01 16:33:33 -07:00
Howard Mao
8983b0e865
hopefully the last fix for AXI -> AHB converter
2016-06-01 15:01:52 -07:00
Howard Mao
a917f554fd
use Wesley's test SRAM for AXI -> AHB converter test
2016-06-01 11:40:59 -07:00
Howard Mao
53a0e6cb9c
another fix for AXI -> AHB converter
2016-06-01 11:35:36 -07:00
Howard Mao
e8408f0a8a
fix HastiRAM
2016-06-01 10:33:59 -07:00
Howard Mao
d0988902f2
fix NASTI -> HASTI bridge
2016-05-31 19:47:50 -07:00
Howard Mao
8f269b2eec
stall for more cycles in Hasti test
2016-05-31 19:46:42 -07:00
Andrew Waterman
1311e78d3f
Add blocking D$ flush support
2016-05-31 19:28:41 -07:00
Andrew Waterman
51379621d6
Flush blocking D$ on FENCE.I
2016-05-31 19:27:28 -07:00
Andrew Waterman
6d82c0d156
Add M_FLUSH_ALL command
2016-05-31 19:25:31 -07:00
Howard Mao
50e3caef36
get rid of Zscale file I missed last time
2016-05-31 14:33:38 -07:00
Andrew Waterman
44a216038f
Use more generic TileLinkWidthAdapter
2016-05-27 13:38:13 -07:00
Andrew Waterman
56897f707a
Don't rely on Mux1H output when no inputs are hot
2016-05-27 13:38:01 -07:00
Andrew Waterman
3ee5144923
Fix TLB tag check logic when ASIDs are present
2016-05-27 12:24:17 -07:00
Andrew Waterman
056d7ec93a
Drive hmastlock low in Nasti-Hasti converter
2016-05-27 12:23:18 -07:00
Matthew Naylor
2a7e7172a9
Update docs for the trace generator
2016-05-27 10:54:35 +01:00
