The previous crossbar had the following bugs:
1. a bursting master could be preempted
the AHB-lite spec requires a slave receive the entire burst
2. a waited master could be replaced
the AHB-lite spec requires haddr/etc to remain unchanged
3. hmastlock did no ensure exclusive access
atomic operations could be pre-empted
When RocketChip has a single memory configuration I want to ensure no extra
hardware is being generated by only instantiating a NastiMemoryInterconnect
rather than a NastiMemorySelector, which I believe will insert a Mux with 0
when there is only one config (because there aren't any 0-width wires allowed).
On Hurricane we want to be able to support multiple memory channels but have a
fallback to fewer, since the full configuration is going to require a
complicated FPGA setup. This adds another sort of interconnect that can switch
between having different numbers of top-level memory channels active at chip
boot time.
This interconnect is a bit funny: changing the select input when there is
memory traffic is a bad idea. This is fine for this use case, since we really
only care about changing the memory configuration at boot time -- since it'll
scramble the memory of the machine it's not so useful, anyway.
The advantage is that we don't have to have a full 8x8 Nasti crossbar in our
chip, which would be fairly expensive. Changing the crossbar would garble
memory as well, so it's not like it would add any extra functionality.
Without this it's really hard to read the IllegalArgumentException that you get
if you subclass ParamaterizedBundle and don't define a matching cloneType().
Since we're separating memory and MMIO traffic in the L1 to L2 network,
we won't need to route between memory and MMIO at the AXI interconnect.
This means we can have separate (and simpler) AXI interconnects for
each. One consequence of this is that the starting address of the IO
interconnect can no longer be assumed to be 0 by default.
