History

Howard Mao bfdf5a538a Separate memory interconnect from IO interconnect. Since we're separating memory and MMIO traffic in the L1 to L2 network, we won't need to route between memory and MMIO at the AXI interconnect. This means we can have separate (and simpler) AXI interconnects for each. One consequence of this is that the starting address of the IO interconnect can no longer be assumed to be 0 by default.		2016-02-02 13:14:04 -08:00
..
project	source and build files. source code pulled from uncore and zscale repos	2015-07-29 18:02:58 -07:00
src/main/scala	Separate memory interconnect from IO interconnect.	2016-02-02 13:14:04 -08:00
.gitignore	Initial commit	2015-07-28 15:52:07 -07:00
build.sbt	Add ability to generate libraryDependency on cde.	2015-10-22 09:52:26 -07:00
LICENSE	Update LICENSE	2015-07-28 16:07:30 -07:00
README.md	Update README.md	2015-07-28 16:20:18 -07:00

README.md

junctions

A repository for peripheral components and IO devices associated with the RocketChip project.

To uses these modules, include this repo as a git submodule within the your chip repository and add it as Project in your chip's build.scala. These components are only dependent on Chisel, i.e.

lazy val junctions = project.dependsOn(chisel)