Chisel3 compatibility fix
No need for a Vec here.
This commit is contained in:
parent
c8fa7c43a9
commit
335fb73120
@ -560,10 +560,11 @@ class NastiRecursiveInterconnect(
|
||||
err_slave.io <> xbarSlave
|
||||
} else {
|
||||
val subSlaves = submap.countSlaves
|
||||
val outputs = Vec(io.slaves.drop(slaveInd).take(subSlaves))
|
||||
val outputs = io.slaves.drop(slaveInd).take(subSlaves)
|
||||
val ic = Module(new NastiRecursiveInterconnect(1, subSlaves, submap, start))
|
||||
ic.io.masters.head <> xbarSlave
|
||||
outputs <> ic.io.slaves
|
||||
for ((o, s) <- outputs zip ic.io.slaves)
|
||||
o <> s
|
||||
slaveInd += subSlaves
|
||||
}
|
||||
case MemChannels(_, nchannels, _) =>
|
||||
|
Loading…
Reference in New Issue
Block a user