6b39db8ce6
On Hurricane we want to be able to support multiple memory channels but have a fallback to fewer, since the full configuration is going to require a complicated FPGA setup. This adds another sort of interconnect that can switch between having different numbers of top-level memory channels active at chip boot time. This interconnect is a bit funny: changing the select input when there is memory traffic is a bad idea. This is fine for this use case, since we really only care about changing the memory configuration at boot time -- since it'll scramble the memory of the machine it's not so useful, anyway. The advantage is that we don't have to have a full 8x8 Nasti crossbar in our chip, which would be fairly expensive. Changing the crossbar would garble memory as well, so it's not like it would add any extra functionality. |
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| build.sbt | ||
| LICENSE | ||
| README.md | ||
junctions
A repository for peripheral components and IO devices associated with the RocketChip project.
To uses these modules, include this repo as a git submodule within the your chip repository and add it as Project in your chip's build.scala. These components are only dependent on Chisel, i.e.
lazy val junctions = project.dependsOn(chisel)