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riscv
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rocket-chip
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4c07aedfad25a8964f2001c6aaf2eb2733fed737
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Albert Ou
4c07aedfad
Rewrite BRAMSlave to infer a single BRAM instance
2016-07-05 14:21:21 -07:00
uncore
Rewrite BRAMSlave to infer a single BRAM instance
2016-07-05 14:21:21 -07:00
Description
Rocket Chip Generator (
https://github.com/freechipsproject/rocket-chip
)
13
MiB
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%