Andrew Waterman
|
110e53cb48
|
Revert "Add early out to multiplier"
This broke recently and I don't have time to figure out why.
|
2013-09-15 04:15:32 -07:00 |
|
Andrew Waterman
|
88d1c47665
|
don't disassemble within chisel
|
2013-09-15 04:14:45 -07:00 |
|
Andrew Waterman
|
f12bbc1e43
|
working RoCC AccumulatorExample
|
2013-09-14 22:34:53 -07:00 |
|
Andrew Waterman
|
18968dfbc7
|
Move store data generation into cache
|
2013-09-14 16:15:07 -07:00 |
|
Andrew Waterman
|
a0cb711451
|
Start adding RoCC
|
2013-09-14 15:31:50 -07:00 |
|
Andrew Waterman
|
d053bdc89f
|
Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
|
2013-09-12 22:34:38 -07:00 |
|
Andrew Waterman
|
1edb1e2a0a
|
Ignore LSB of PC
|
2013-09-12 17:55:58 -07:00 |
|
Andrew Waterman
|
59f5358435
|
Implement AQ/RL; move fence logic out of cache
|
2013-09-12 16:07:30 -07:00 |
|
Andrew Waterman
|
243c4ae342
|
sync up rocket with new isa
|
2013-09-12 03:44:38 -07:00 |
|
Andrew Waterman
|
95dd0d8be1
|
Remove DebugIO/error mode
|
2013-09-11 20:15:21 -07:00 |
|
Henry Cook
|
f9b85d8158
|
NetworkIOs no longer use thunks
|
2013-09-10 16:15:19 -07:00 |
|
Henry Cook
|
d06e24ac24
|
new enum syntax
|
2013-09-10 10:51:35 -07:00 |
|
Stephen Twigg
|
cfbfa6b895
|
Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.
|
2013-09-05 19:22:34 -07:00 |
|
Stephen Twigg
|
d896ccbd43
|
Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/htif.scala
|
2013-09-05 16:11:53 -07:00 |
|
Andrew Waterman
|
b9f6e1a7ec
|
Don't update BTB when garbage was fetched
|
2013-08-26 14:53:04 -07:00 |
|
Yunsup Lee
|
44e92edf92
|
fix scr parameterization bug
|
2013-08-24 22:42:51 -07:00 |
|
Andrew Waterman
|
3895b75a56
|
Support non-power-of-2 BTBs; prefer invalid entries
|
2013-08-24 17:33:11 -07:00 |
|
Yunsup Lee
|
2ca5127785
|
parameterize number of SCRs
|
2013-08-24 15:47:14 -07:00 |
|
Andrew Waterman
|
daf23b8f79
|
Add early out to multiplier
|
2013-08-24 14:44:23 -07:00 |
|
Andrew Waterman
|
67f80ba4b2
|
Stall div/mul writeback until WB slot is free
|
2013-08-24 14:44:17 -07:00 |
|
Andrew Waterman
|
d1b5076fee
|
Don't update BTB when garbage was fetched
|
2013-08-24 14:44:11 -07:00 |
|
Andrew Waterman
|
52e31f3298
|
Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
|
2013-08-24 14:44:04 -07:00 |
|
Andrew Waterman
|
d4a0db4575
|
Reflect ISA changes
|
2013-08-24 14:43:55 -07:00 |
|
Henry Cook
|
ff7b486006
|
standardized sbt build
|
2013-08-15 18:13:19 -07:00 |
|
Henry Cook
|
ae02ebd153
|
Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
Conflicts:
src/core.scala
src/ctrl.scala
src/dpath_util.scala
src/fpu.scala
src/nbdcache.scala
src/tile.scala
|
2013-08-15 16:35:27 -07:00 |
|
Henry Cook
|
3a266cbbfa
|
final Reg changes
|
2013-08-15 15:28:15 -07:00 |
|
Henry Cook
|
b570435847
|
Reg standardization
|
2013-08-13 17:50:02 -07:00 |
|
Henry Cook
|
858169917e
|
removed dummy DNCs handled by pruning
|
2013-08-12 22:34:46 -07:00 |
|
Henry Cook
|
d9b3c7cfc8
|
Moved RenEn to ChiselUtil
|
2013-08-12 22:18:25 -07:00 |
|
Huy Vo
|
387cf0ebe0
|
reset -> resetVal, getReset -> reset
|
2013-08-12 20:51:54 -07:00 |
|
Henry Cook
|
1a9e43aa11
|
initial attempt at upgrade
|
2013-08-12 10:39:11 -07:00 |
|
Henry Cook
|
de313d97de
|
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
|
2013-08-02 16:30:09 -07:00 |
|
Henry Cook
|
4eaab214d2
|
Fold uncore constants into TileLinkConfiguration, update coherence API
|
2013-08-02 16:29:51 -07:00 |
|
Henry Cook
|
bef6c1db35
|
minor nbdcache cleanup
|
2013-08-02 16:29:37 -07:00 |
|
Stephen Twigg
|
3132db4f90
|
Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.
|
2013-07-30 16:36:28 -07:00 |
|
Henry Cook
|
9abdf4e154
|
Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
|
2013-07-23 20:27:58 -07:00 |
|
Henry Cook
|
5c00d0a030
|
new tilelink arbiter type
|
2013-07-09 15:31:46 -07:00 |
|
Andrew Waterman
|
7cc53c7725
|
clean up Str
|
2013-06-15 00:45:53 -07:00 |
|
Andrew Waterman
|
95c5147dc5
|
Add RISC-V instruction disassembler
|
2013-06-13 10:31:04 -07:00 |
|
Henry Cook
|
569d8fd796
|
Merge branch 'tilelink-data'
|
2013-05-23 14:14:40 -07:00 |
|
Henry Cook
|
12205b9684
|
remove obsolete config file reader prototype
|
2013-05-23 14:09:03 -07:00 |
|
Andrew Waterman
|
fe9adfe71b
|
Simplify and correct integer multiplier
|
2013-05-22 17:27:50 -07:00 |
|
Yunsup Lee
|
11133d6d4c
|
clock gate s2 registers in the frontend
|
2013-05-21 18:59:21 -07:00 |
|
Yunsup Lee
|
c837c1d800
|
fix bug in previous JALR commit
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
|
2013-05-21 18:28:44 -07:00 |
|
Henry Cook
|
69b508ff39
|
ported caches and htif to use new tilelink
|
2013-05-21 17:21:04 -07:00 |
|
Andrew Waterman
|
28f914c3f2
|
don't JALR to speculatively-bypassed addresses
Technically not necessary, but probably improves performance.
|
2013-05-21 16:56:58 -07:00 |
|
Yunsup Lee
|
dcde377303
|
Fix DM I$ deadlock
BTB predictions were causing infinite miss loops
|
2013-05-20 15:22:58 -07:00 |
|
Andrew Waterman
|
3a1b5f01b2
|
don't take interrupts while they're disabled!
a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
|
2013-05-19 23:27:47 -07:00 |
|
Andrew Waterman
|
6eb4c2542a
|
comment out I$ assert for now
|
2013-05-18 18:09:23 -07:00 |
|
Andrew Waterman
|
1dab984231
|
use UFix instead of Bits for arithmetic
|
2013-05-18 00:45:29 -07:00 |
|