Henry Cook
224e286dd3
New uncore config objects. Backends get their own file. Simplify fpga uncore.
2014-04-26 19:46:11 -07:00
Henry Cook
52c6de5641
DRAMSideLLCLike trait. TSHRFile. New L2 config objects.
2014-04-26 19:11:36 -07:00
Henry Cook
519b2ea2b6
New metadata result trait
2014-04-26 19:08:56 -07:00
Henry Cook
3d4273954a
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:19:25 -07:00
Henry Cook
1b156c6db9
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:18:21 -07:00
Henry Cook
1163131d1e
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:17:05 -07:00
Henry Cook
3f53d532c2
uniquify tilelink conf val name for easier subtyping
2014-04-26 14:58:38 -07:00
Henry Cook
fbf6e44376
fix connection error in fpga uncore
2014-04-24 11:58:59 -07:00
Henry Cook
1e062d1bcd
bump rocket, uncore
2014-04-23 16:27:34 -07:00
Henry Cook
f8f29c69b8
MetaData & friends moved to uncore/
2014-04-23 16:24:20 -07:00
Henry Cook
fc825c7103
MetaData & friends moved to uncore/
2014-04-23 16:23:51 -07:00
Henry Cook
f4d326b8d7
Prep in HellaCache for extracting MetaData to uncore
2014-04-23 15:43:31 -07:00
Henry Cook
83a3cb4999
bump rocket, uncore
2014-04-22 17:32:39 -07:00
Henry Cook
39681303b8
beginning of l2 cache
2014-04-22 16:58:15 -07:00
Henry Cook
5c62cff2ce
put replacement policy in uncore and minor nbdcache cleanups
2014-04-22 16:53:20 -07:00
Yunsup Lee
2fefbdd453
fixes to physical design flow
2014-04-21 21:36:39 -07:00
Henry Cook
cfd6748318
patches to make FAME1/dram IOs compile with up-to-date chisel (bumped)
2014-04-21 17:26:33 -07:00
Henry Cook
1bf5439f0b
include new mm test in benchmarks
2014-04-18 18:05:30 -07:00
Henry Cook
5613dc7d1b
replaced Lists with Vecs
2014-04-18 17:26:56 -07:00
Andrew Waterman
09e2ec1f9e
Fix sign of remainder when dividing by zero
...
h/t chris
2014-04-18 16:32:57 -07:00
Jim Lawson
bf2ff7804e
Add chisel-dependent.sbt for -DchiselVersion="latest.release"
...
If -DchiselVersion is specified on the command line, add the
appropriate chisel library to libraryDependencies.
2014-04-17 17:01:40 -07:00
Henry Cook
1fa505f9ff
remove superfluous AVec object
2014-04-16 17:19:32 -07:00
Andrew Waterman
3520620fbd
Remove D$ -> BTB path
2014-04-15 23:05:02 -07:00
Andrew Waterman
de492b3cf7
Fix critical path through integer scoreboard
2014-04-15 21:28:13 -07:00
Yunsup Lee
e4c97e7a57
push tools/tests
2014-04-14 21:18:22 -07:00
Henry Cook
691aa4107e
bump rocket
2014-04-14 17:13:57 -07:00
Henry Cook
444d0449e3
io.cnt bug in serializer
2014-04-14 17:13:13 -07:00
Henry Cook
2cb4dbae39
Refactored uncore constants and tilelink data
2014-04-10 13:19:50 -07:00
Henry Cook
5a5f69bfca
finished uncore constant/tilelink data refactor
2014-04-10 13:13:46 -07:00
Henry Cook
b1df49ba30
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
2014-04-10 12:35:43 -07:00
Henry Cook
fbca7c6bb3
refactor ioMem and associcated constants. merge Aqcuire and AcquireData
2014-04-10 12:35:43 -07:00
Henry Cook
1da8ef2ddf
Added serdes to decouple cache row size from tilelink data size
2014-04-10 12:34:12 -07:00
Henry Cook
910b3b203a
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
2014-04-10 12:32:44 -07:00
Henry Cook
ebdc0a2692
merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
2014-04-10 12:09:52 -07:00
Stephen Twigg
cac04afc25
Push riscv-tests, riscv-tools. Repository now consistent such that all tests build, pass in spike, in emulator, and in RTL.
2014-04-08 22:14:16 -07:00
Stephen Twigg
f643d38672
Push rocket, riscv-tests, riscv-tools to consistent state (toolchain rebuild required)
2014-04-08 16:50:52 -07:00
Stephen Twigg
e90f2484aa
Sync with riscv-opcodes (csr register mapping)
2014-04-08 15:48:37 -07:00
Andrew Waterman
fb8c7d3da5
Push rocket
2014-04-07 23:49:06 -07:00
Andrew Waterman
3ed8adf032
Add early out for MUL[W] (not MULH[[S]U])
2014-04-07 23:48:02 -07:00
Andrew Waterman
927287da34
Bypass RAS push/pop
2014-04-07 23:47:53 -07:00
Andrew Waterman
817517c663
Better branch prediction
2014-04-07 16:08:06 -07:00
Andrew Waterman
f235fa0db6
Move branch resolution to M stage
2014-04-07 15:58:49 -07:00
Andrew Waterman
db59fc65ab
Add return address stack
2014-04-01 15:01:27 -07:00
Henry Cook
56f515c255
first steps in uncore constant/tilelink data refactor
2014-03-30 09:21:08 -07:00
Andrew Waterman
e3b12e0b85
Make BTB more complexity-effective
...
BTB entries reference a small number of unique pages, so we separate the
storage of pages from indices. This makes much larger BTBs feasible. It's
easy to exacerbate cycle time this way, so one-hot encoding is used as needed.
2014-03-25 05:22:04 -07:00
Andrew Waterman
804b09c8c5
Frontend QoR tweaks
2014-03-25 05:20:24 -07:00
Andrew Waterman
6465e2df14
Make Int -> Bool conversions explicit
2014-03-24 04:36:53 -07:00
Andrew Waterman
1b030777ce
Remove vestigial control signal
2014-03-24 04:36:12 -07:00
Donggyu Kim
16274a84b6
update fpga testbench
2014-03-21 16:21:15 -07:00
Jim Lawson
a228dbfa0d
Revert "Update library dependencies (jenkins builds)"
...
This reverts commit e7a12143d0bfe8b3b4a4dcc78d119a89553ade8c.
2014-03-20 10:40:05 -07:00
