Andrew Waterman
|
e496cd7584
|
use Mem to implement queues to speed things up
|
2012-07-13 21:48:05 -07:00 |
|
Huy Vo
|
fd95159837
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
Andrew Waterman
|
bac82762d3
|
use only one (wide) tag ram for set assoc. caches
|
2012-07-12 14:50:12 -07:00 |
|
Andrew Waterman
|
429fcbed8e
|
fix some LLC bugs
|
2012-07-11 17:56:39 -07:00 |
|
Andrew Waterman
|
f645fb4dd7
|
add L2$
It still has performance bugs but no correctness bugs AFAIK.
|
2012-07-10 05:23:29 -07:00 |
|
Andrew Waterman
|
5035374f36
|
update to new chisel
|
2012-07-08 17:59:41 -07:00 |
|
Andrew Waterman
|
39d198ecdc
|
fix htif handling of large memory reads
|
2012-06-26 19:12:11 -07:00 |
|
Andrew Waterman
|
4e5f874266
|
update to new chisel/hwacha
|
2012-06-08 00:13:14 -07:00 |
|
Huy Vo
|
a99cebb483
|
ioDecoupled -> FIFOIO, ioPipe -> PipeIO
|
2012-06-06 18:22:56 -07:00 |
|
Huy Vo
|
04304fe788
|
moving util out into Chisel standard library
|
2012-06-06 12:51:26 -07:00 |
|
Huy Vo
|
c975c21e44
|
views removed
|
2012-06-06 12:51:26 -07:00 |
|
Andrew Waterman
|
943b6d0616
|
remove debug println
|
2012-06-06 02:48:48 -07:00 |
|
Andrew Waterman
|
7f6319047e
|
update to new scala/chisel/Mem
|
2012-06-06 02:47:22 -07:00 |
|
Huy Vo
|
7408c9ab69
|
removing wires
|
2012-05-24 10:42:39 -07:00 |
|
Huy Vo
|
181b20d69c
|
working vec unit with pvfb
|
2012-05-24 10:38:14 -07:00 |
|
Andrew Waterman
|
faee45bf4c
|
fix setpcr/clearpcr not writing rd
|
2012-05-21 07:25:35 -07:00 |
|
Yunsup Lee
|
c9602a0d2e
|
fix vector control decode bug
|
2012-05-15 10:26:37 -07:00 |
|
Gage W Eads
|
d0bc995c88
|
Fixed IRQ_IPI -> IRQ_TIMER typo
|
2012-05-14 22:25:12 -07:00 |
|
Andrew Waterman
|
a2f6d01c1b
|
add programmable coreid register
|
2012-05-09 03:09:22 -07:00 |
|
Andrew Waterman
|
e0e1cd5d32
|
add IPIs and an IPI test
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
|
2012-05-08 22:58:00 -07:00 |
|
Henry Cook
|
87cbae2c8a
|
Removed defunct ioDmem
|
2012-05-07 17:31:39 -07:00 |
|
Andrew Waterman
|
b851f1b34c
|
support maximum-MTU HTIF packets
|
2012-05-03 21:11:43 -07:00 |
|
Andrew Waterman
|
171c87002e
|
reduce HTIF clock divider for now
|
2012-05-03 04:21:11 -07:00 |
|
Andrew Waterman
|
e1f9dc2c1f
|
generalize page table walker
also, don't instantiate vitlb when !HAVE_VEC
|
2012-05-03 02:29:09 -07:00 |
|
Andrew Waterman
|
2d4e5d3813
|
fix pseudo-LRU verilog generation bug
|
2012-05-02 19:31:31 -07:00 |
|
Henry Cook
|
622a801bb1
|
Refactored cpu/cache interface to use nested bundles
|
2012-05-02 11:54:28 -07:00 |
|
Andrew Waterman
|
65ff397122
|
improved instruction decoding
it now makes use of don't-cares by performing logic minimization
|
2012-05-01 20:16:36 -07:00 |
|
Andrew Waterman
|
4cfa6cd9a8
|
force Top.main's return type to Unit
|
2012-05-01 19:55:16 -07:00 |
|
Andrew Waterman
|
5819beed64
|
use parameterized FP units
|
2012-05-01 01:25:43 -07:00 |
|
Andrew Waterman
|
eafdffe125
|
simplify page table walker; speed up emulator
|
2012-05-01 01:24:36 -07:00 |
|
Andrew Waterman
|
c13d3e6f88
|
fix probe tag read-modify-write atomicity violation
|
2012-04-26 02:29:31 -07:00 |
|
Andrew Waterman
|
66f86a2194
|
use pseudo-LRU replacement for TLBs
|
2012-04-26 02:29:30 -07:00 |
|
Andrew Waterman
|
a0378c5d2f
|
remove faulting TLB entry after page fault
this vastly reduces the frequency with which the TLB must be flushed
|
2012-04-26 02:29:30 -07:00 |
|
Andrew Waterman
|
6d8fc74378
|
fix DTLB permissions bug
|
2012-04-26 02:29:30 -07:00 |
|
Henry Cook
|
1ed89f1cab
|
Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle
|
2012-04-24 17:17:42 -07:00 |
|
Henry Cook
|
55e86b5cf4
|
Fixed coherence bug: probe counting for single tile
|
2012-04-24 17:17:13 -07:00 |
|
Henry Cook
|
a39080d0b1
|
Fixed abort bug: xact_abort.ready was not pinned high
|
2012-04-24 17:16:40 -07:00 |
|
Andrew Waterman
|
fb4408b150
|
fix AMO replay/coherence deadlock
|
2012-04-15 22:56:02 -07:00 |
|
Andrew Waterman
|
724735f13f
|
fix writeback bug
|
2012-04-13 03:16:48 -07:00 |
|
Andrew Waterman
|
00d934cfac
|
fix coherence bugs in cache
|
2012-04-12 21:57:37 -07:00 |
|
Henry Cook
|
fef58f1b3a
|
Policy determined by constants. MSI policy added.
|
2012-04-11 17:56:59 -07:00 |
|
Andrew Waterman
|
c0ec3794bf
|
coherence mostly works now
|
2012-04-10 02:22:45 -07:00 |
|
Henry Cook
|
3cdd166153
|
Refactored coherence as member rather than trait. MI and MEI protocols.
|
2012-04-10 00:09:58 -07:00 |
|
Henry Cook
|
9c8f849f50
|
defined abstract coherence traits in base trait, added Incoherent trait, cleaned up incoherent policy
|
2012-04-09 23:29:32 -07:00 |
|
Henry Cook
|
551e09c9d5
|
changed coherence type width names to represent max sizes for all protocols
|
2012-04-09 23:29:32 -07:00 |
|
Henry Cook
|
0b4937f70f
|
changed coherence message type names
|
2012-04-09 23:29:31 -07:00 |
|
Henry Cook
|
ed79ec98f7
|
Refactored coherence better from uncore hub, better coherence function names
|
2012-04-09 23:29:31 -07:00 |
|
Andrew Waterman
|
aee9378712
|
fix coherence bug with multiple probe replies
|
2012-04-09 21:40:35 -07:00 |
|
Huy Vo
|
c9c3bd02bc
|
kill mem stage if fpu nacks in mem stage
|
2012-04-01 17:02:32 -07:00 |
|
Andrew Waterman
|
7f254d9670
|
refine FP bugfixes
|
2012-04-01 14:52:33 -07:00 |
|
Huy Vo
|
c7c35322c2
|
two bug fixes to fpu
|
2012-03-31 22:23:51 -07:00 |
|
Andrew Waterman
|
a09e8d1c55
|
remove I$ prefetcher for now
there's a bug in it, and I don't have time to fix it at the moment.
|
2012-03-27 15:43:56 -07:00 |
|
Andrew Waterman
|
452876af37
|
fence on vvcfg; implement fence.v.g correctly
|
2012-03-27 14:49:00 -07:00 |
|
Yunsup Lee
|
bb704dc0c9
|
fix vector length calc bug, thanks chris and andrew
|
2012-03-27 12:04:07 -07:00 |
|
Andrew Waterman
|
6bda8674bd
|
no dessert tonight :(
|
2012-03-26 23:50:09 -07:00 |
|
Yunsup Lee
|
a70f0414fa
|
fix a workaroundable bug
|
2012-03-26 20:51:54 -07:00 |
|
Yunsup Lee
|
32d95e9594
|
fix -1:0 index problem for direct map case
|
2012-03-26 17:00:01 -07:00 |
|
Andrew Waterman
|
e2fe525fb6
|
remove bug from dessert
|
2012-03-26 14:18:57 -07:00 |
|
Yunsup Lee
|
e6b0e565de
|
turn HAVE_VEC on
|
2012-03-26 01:21:39 -07:00 |
|
Andrew Waterman
|
5f53cd4ac1
|
reduce HTIF width
|
2012-03-25 23:49:59 -07:00 |
|
Andrew Waterman
|
ef505de017
|
reduce HTIF width
|
2012-03-25 23:49:45 -07:00 |
|
Andrew Waterman
|
31f0b600fd
|
add dessert
|
2012-03-25 23:03:20 -07:00 |
|
Andrew Waterman
|
1666d3fbd7
|
loop host.in to host.out during reset
|
2012-03-25 21:45:10 -07:00 |
|
Andrew Waterman
|
f62a02ab54
|
remove dumb stuff in top.scala
|
2012-03-25 21:30:01 -07:00 |
|
Andrew Waterman
|
88bf8a4f23
|
add mem serdes unit
|
2012-03-25 17:03:58 -07:00 |
|
Andrew Waterman
|
7fa93da4f5
|
add backup memory port (disabled for now)
|
2012-03-25 15:49:32 -07:00 |
|
Yunsup Lee
|
1f33f6bb58
|
HAVE_VEC is on
|
2012-03-24 20:54:43 -07:00 |
|
Andrew Waterman
|
86d56ff67b
|
refactor cpu/i$/d$ into Tile (rather than Top)
|
2012-03-24 16:57:28 -07:00 |
|
Andrew Waterman
|
3a487ac89b
|
improve htif<->pcr interface
|
2012-03-24 16:57:28 -07:00 |
|
Andrew Waterman
|
54fa6f660d
|
new supervisor mode
|
2012-03-24 13:03:31 -07:00 |
|
Yunsup Lee
|
65929a62e3
|
fix reset value for appvl
|
2012-03-22 15:32:04 -07:00 |
|
Yunsup Lee
|
aaed0241af
|
get rid of vxcptwait
|
2012-03-21 15:09:04 -07:00 |
|
Yunsup Lee
|
023734175d
|
now fence stalls in decode
|
2012-03-20 17:10:05 -07:00 |
|
Yunsup Lee
|
e450e3aa40
|
fix irt counter bug regarding vector stuff
|
2012-03-20 17:09:54 -07:00 |
|
Yunsup Lee
|
7d7d7f49f9
|
change the tlb arbiter to a round robing one
|
2012-03-20 15:21:36 -07:00 |
|
Yunsup Lee
|
1cddd5de56
|
fix amo locking up problem
|
2012-03-20 02:16:28 -07:00 |
|
Yunsup Lee
|
56cb9b7a63
|
fix bug in coherence hub, specifically in abort handling logic
|
2012-03-20 02:16:28 -07:00 |
|
Yunsup Lee
|
c036fff79c
|
fix id interrupt signal
|
2012-03-19 15:13:57 -07:00 |
|
Yunsup Lee
|
0edea00166
|
now HAVE_VEC is true, since it passes the emulator
|
2012-03-19 03:10:00 -07:00 |
|
Yunsup Lee
|
264732556f
|
fixes to match verilog X semantics
|
2012-03-19 03:10:00 -07:00 |
|
Andrew Waterman
|
bd27d0fab2
|
can now take interrupts on stalled instructions
|
2012-03-19 01:02:06 -07:00 |
|
Andrew Waterman
|
2ed0be65f9
|
fix RRArbiter
|
2012-03-19 00:19:33 -07:00 |
|
Yunsup Lee
|
ba06cd953e
|
add chosen
|
2012-03-18 20:43:17 -07:00 |
|
Andrew Waterman
|
c4a91303fb
|
update vector fence names and encoding
|
2012-03-18 20:42:38 -07:00 |
|
Yunsup Lee
|
2a01f558ba
|
fix unmasked valid bug in ctrl_vec
|
2012-03-18 19:55:24 -07:00 |
|
Yunsup Lee
|
98e10ddc3c
|
update vector exception instructions
|
2012-03-18 16:36:12 -07:00 |
|
Yunsup Lee
|
7493d55d3f
|
add pf fault handling
|
2012-03-18 15:06:39 -07:00 |
|
Yunsup Lee
|
62ada5ea9e
|
hookup vitlb ptw port
|
2012-03-17 23:01:06 -07:00 |
|
Yunsup Lee
|
b793d63182
|
no vector interrupt masking
|
2012-03-17 23:01:06 -07:00 |
|
Yunsup Lee
|
8a4f95e617
|
changes to xcpt handling
|
2012-03-17 17:50:37 -07:00 |
|
Yunsup Lee
|
8c50c81b81
|
drop vec_irq_aux pcr register, now everything goes through badvaddr
|
2012-03-17 14:03:57 -07:00 |
|
Yunsup Lee
|
3b4680a834
|
add vitlb exception port
|
2012-03-17 14:03:33 -07:00 |
|
Andrew Waterman
|
a47eeb9571
|
retime D$ bypass into beginning of EX stage
|
2012-03-16 18:35:54 -07:00 |
|
Andrew Waterman
|
6c26921766
|
reduce D$ critical path through page table walker
costs an extra cycle per page table level to resolve a TLB miss. too bad.
|
2012-03-16 18:35:54 -07:00 |
|
Yunsup Lee
|
d38603a4ee
|
change number of tlb entries
|
2012-03-16 17:08:03 -07:00 |
|
Andrew Waterman
|
f0157b9e2a
|
fix coherence bug
popping wrong store dependence queue
|
2012-03-16 01:24:07 -07:00 |
|
Andrew Waterman
|
cfca2d1411
|
clean up cache interfaces; avoid reserved keywords
|
2012-03-16 00:44:16 -07:00 |
|
Andrew Waterman
|
820884c7e6
|
fix probes for smaller cache sizes
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
|
2012-03-15 23:08:30 -07:00 |
|
Andrew Waterman
|
4684171ac6
|
fix fence.i for associative caches
|
2012-03-15 21:23:21 -07:00 |
|
Andrew Waterman
|
2b0bc8df2b
|
use divided clk for htif. UDPATE YOUR FESVR
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
|
2012-03-15 18:36:51 -07:00 |
|