defined abstract coherence traits in base trait, added Incoherent trait, cleaned up incoherent policy
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@ -50,59 +50,99 @@ object cpuCmdToRW {
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}
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}
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trait CoherencePolicy { }
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trait CoherencePolicy {
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def isHit (cmd: Bits, state: UFix): Bool
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def isValid (state: UFix): Bool
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trait ThreeStateIncoherence extends CoherencePolicy {
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool
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def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool
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def needsWriteback (state: UFix): Bool
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def newStateOnHit(cmd: Bits, state: UFix): UFix
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def newStateOnCacheControl(cmd: Bits): UFix
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def newStateOnWriteback(): UFix
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def newStateOnFlush(): UFix
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def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix
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def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix
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def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits
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def getTransactionInitTypeOnWriteback(): Bits
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply
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def hasData (reply: ProbeReply): Bool
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def hasData (init: TransactionInit): Bool
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def hasData (reply: TransactionReply): Bool
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool
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def getTransactionReplyType(x_type: UFix, count: UFix): Bits
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def getProbeRequestType(x_type: UFix, global_state: UFix): UFix
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def needsMemRead(x_type: UFix, global_state: UFix): Bool
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def needsMemWrite(x_type: UFix, global_state: UFix): Bool
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def needsAckReply(x_type: UFix, global_state: UFix): Bool
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}
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trait IncoherentPolicy extends CoherencePolicy {
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// UNIMPLEMENTED
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = state
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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reply.p_type := UFix(0)
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reply.global_xact_id := UFix(0)
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reply
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}
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def hasData (reply: ProbeReply) = Bool(false)
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = Bool(false)
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def getTransactionReplyType(x_type: UFix, count: UFix): Bits = Bits(0)
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def getProbeRequestType(x_type: UFix, global_state: UFix): UFix = UFix(0)
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def needsMemRead(x_type: UFix, global_state: UFix): Bool = Bool(false)
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def needsMemWrite(x_type: UFix, global_state: UFix): Bool = Bool(false)
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def needsAckReply(x_type: UFix, global_state: UFix): Bool = Bool(false)
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}
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trait ThreeStateIncoherence extends IncoherentPolicy {
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val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
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val xactInitReadShared = UFix(0, 2)
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val xactInitReadExclusive = UFix(1, 2)
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val xactInitWriteUncached = UFix(3, 2)
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val xactReplyReadShared = UFix(0, X_REP_TYPE_MAX_BITS)
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val xactReplyReadExclusive = UFix(1, X_REP_TYPE_MAX_BITS)
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val xactReplyWriteUncached = UFix(3, X_REP_TYPE_MAX_BITS)
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val probeRepInvalidateAck = UFix(3, P_REP_TYPE_MAX_BITS)
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val xactInitReadClean :: xactInitReadDirty :: xactInitWriteback :: Nil = Enum(3){ UFix() }
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val xactReplyData :: xactReplyAck :: Nil = Enum(2){ UFix() }
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val probeRepInvalidateAck :: Nil = Enum(1){ UFix() }
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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( state === tileClean || state === tileDirty)
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}
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def isHit ( cmd: Bits, state: UFix): Bool = (state === tileClean || state === tileDirty)
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def isValid (state: UFix): Bool = state != tileInvalid
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def isValid (state: UFix): Bool = {
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state != tileInvalid
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}
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit) = Bool(false)
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def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = state === tileDirty
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def needsWriteback (state: UFix): Bool = state === tileDirty
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def needsWriteback (state: UFix): Bool = {
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state === tileDirty
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}
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def newStateOnWriteback() = tileInvalid
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def newStateOnCacheControl(cmd: Bits) = tileInvalid
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def newState(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, Mux(read, Mux(state === tileDirty, tileDirty, tileClean), state))
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}
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def newStateOnHit(cmd: Bits, state: UFix): UFix = newState(cmd, state)
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def newStateOnCacheControl(cmd: Bits) = tileInvalid //TODO
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def newStateOnWriteback() = tileInvalid
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def newStateOnFlush() = tileInvalid
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def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit) = {
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MuxLookup(incoming.x_type, tileInvalid, Array(
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xactReplyData -> Mux(outstanding.x_type === xactInitReadDirty, tileDirty, tileClean),
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xactReplyAck -> tileInvalid
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))
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}
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write || cmd === M_PFW, xactInitReadExclusive, xactInitReadShared)
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Mux(write || cmd === M_PFW, xactInitReadDirty, xactInitReadClean)
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}
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def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, xactInitReadExclusive, outstanding.x_type)
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Mux(write, xactInitReadDirty, outstanding.x_type)
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}
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = Bool(false)
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def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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Mux(outstanding.x_type === xactInitReadExclusive, tileDirty, tileClean)
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = state
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def newProbeReply (incoming: ProbeRequest, has_data: Bool): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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reply.p_type := probeRepInvalidateAck
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reply.global_xact_id := UFix(0)
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reply
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}
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def probeReplyHasData (reply: ProbeReply): Bool = Bool(false)
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def transactionInitHasData (init: TransactionInit): Bool = (init.x_type === xactInitWriteUncached)
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def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteback //TODO
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def getTransactionInitTypeOnWriteback(): Bits = xactInitWriteback
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def hasData (init: TransactionInit): Bool = (init.x_type === xactInitWriteback)
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def hasData (reply: TransactionReply) = (reply.x_type === xactReplyData)
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}
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trait FourStateCoherence extends CoherencePolicy {
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@ -251,7 +251,7 @@ abstract class CoherenceHub(ntiles: Int) extends Component with CoherencePolicy
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class CoherenceHubNull extends CoherenceHub(1) with ThreeStateIncoherence
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{
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val x_init = io.tiles(0).xact_init
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val is_write = x_init.bits.x_type === xactInitWriteUncached
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val is_write = x_init.bits.x_type === xactInitWriteback
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x_init.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp
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io.mem.req_cmd.valid := x_init.valid && !(is_write && io.mem.resp.valid)
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io.mem.req_cmd.bits.rw := is_write
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@ -260,7 +260,7 @@ class CoherenceHubNull extends CoherenceHub(1) with ThreeStateIncoherence
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io.mem.req_data <> io.tiles(0).xact_init_data
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val x_rep = io.tiles(0).xact_rep
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x_rep.bits.x_type := Mux(io.mem.resp.valid, xactReplyReadExclusive, xactReplyWriteUncached)
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x_rep.bits.x_type := Mux(io.mem.resp.valid, xactReplyData, xactReplyAck)
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x_rep.bits.tile_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, x_init.bits.tile_xact_id)
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x_rep.bits.global_xact_id := UFix(0) // don't care
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x_rep.bits.data := io.mem.resp.bits.data
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