riscv/rocket-chip
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Author SHA1 Message Date
Wesley W. Terpstra aabd17d935 rocketchip: must create bundles within Module scope 
1. Bundles be created after base class Module constructor runs
2. Bundles must be created before Module(...) runs

Solution: pass a bundle constructor to the cake base class

Require the constructor to take a parameter so people don't use it by
accident; they should get a type error.

Consistently name all the cake arguments with an _io, _coreplex, _outer,
so that they don't shadow the base class variables you should be using.
 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra d52615c39e coreplex: one IntNode per tile 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra e97844f71e coreplex: make it possible to override the ConfigString 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 4de1822470 rocketchip: avoid using the nearly defunct GlobalAddrMap 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 688e1bffdf rocketchip: pull rtcTick out of the coreplex 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 5bca13ebdb rocketchip: use self-type constraints 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra d51b0b5c02 rocketchip: use self-type 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 841a31479a coreplex: fix TinyConfig 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra ba529c3716 rocketchip: use TileLink2 interrupts 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 6505431eac coreplex: use self-type constraints 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra ac886026e6 rocketchip: reduce number of type parameters 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 043ed48c8c tilelink2 HintHandler: delay answers to help TL1 legacy clients 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 72a7948ad2 rocketchip Periphery: move atomics before WidthWidget => 64-bit AMOs 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 015c3b862a diplomacy: print out bus widths on edges in agent graph 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 92ee498521 rocket scratchpad: support atomics 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 0cc00e7616 regressions: test scratchpad 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra d2e9fa8ec6 Plic: remove path from ready to bits 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 545154c1c3 groundtest: make it happy with TL2 addressing 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 9a26cb7ec7 Debug: mark the debug device executable 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra e9725aea2f rocketchip: all of the address map now comes from TL2 2016-10-31 11:42:44 -07:00
Wesley W. Terpstra 401fd378b4 rocketchip: include devices from cbus in ConfigString 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra b68bc449e7 rocket: put a Fragmenter infront of the scratchpad 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra a73aa351ca rocketchip: fix all clock crossings 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra 825c253a72 rocketchip: move TL2 and cake pattern into Coreplex 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra 89139a9492 Plic: split constants from variables used in config string 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra 11121b6f4c rocket: convert scratchpad to TL2 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra dddb50a942 BuildTiles: convert to LazyTile 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra f8a0829134 rocketchip: remove clint; it moves into coreplex 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra b99662796d PLIC: converted to TL2 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra bddfa4d69b Debug: make address configurable 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra c3dacca39a rocketchip: remove pbus; TL2 has swallowed it completely 2016-10-31 11:42:08 -07:00
Wesley W. Terpstra 3df797fcab rocketchip: replace TL1 MMIO with an example of TL2 MMIO 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 650f6fb23f diplomacy: add BlindNodes for use as external ports 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 0edcd3304a diplomacy Nodes: leave flipping to the MixedNode implementation 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 082f338432 diplomacy Nodes: remove useless indirection 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra ec2d23b8b7 rocketchip: Bundle-slices need access to the outer LazyModule 
We need this change in order for some ports to use parameters that result
from LazyModule diplomacy.

Now you can eat your cake too!
 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 0ae45d0f24 rocketchip: bundle (=> B) need not be delayed; Module is constructed later 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 0dbda2f07d rocketchip: remove obsolete pDevices used during TL1=>2 migration 2016-10-31 11:41:18 -07:00
Wesley W. Terpstraandmwachs5 a807c922d0 diplomacy: take names from the outermost common node 2016-10-25 15:58:09 -07:00
Wesley W. Terpstraandmwachs5 fee67c4abf diplomacy: add methods to find {out,in}ner-most common node 2016-10-25 15:58:09 -07:00
Wesley W. Terpstraandmwachs5 67ab27f5a5 diplomacy: guess the LazyModule name from the containing class 2016-10-25 15:58:09 -07:00
Wesley W. TerpstraandGitHub 4d50733548 tilelink2 ToAXI4: use helper method for a_last (#418) 2016-10-25 10:16:42 -07:00
Wesley W. TerpstraandGitHub 7dc97674d6 rocketchip: include an socBus between l1tol2 and periphery (#415) 
Sometimes we have high performance devices that go inbetween.
 2016-10-24 23:56:09 -07:00
Wesley W. TerpstraandGitHub a5ac106bb8 axi4 ToTL: fix decode error arbitration (#417) 
When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.

This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
 2016-10-24 22:15:19 -07:00
Wesley W. TerpstraandGitHub 4c815f7958 tilelink2 Parameters: fix {contains,supports}Safe (#416) 
When there is only one manager, you still want to know if the address
was wrong on the link to that manager!
 2016-10-24 20:37:04 -07:00
Wesley W. TerpstraandGitHub 8bfd6bcd4d axi4: ensure we accept AR before reporting R (#411) 2016-10-21 21:02:05 -07:00
Wesley W. TerpstraandGitHub c8fc05d154 Merge pull request #402 from ucb-bar/axi4-slave 
AXI4=>TL2 converter
 2016-10-17 10:34:29 -07:00
Wesley W. Terpstra 7c334e3c34 axi4 ToTL: shorter critical path on Q.bits if errors go first 2016-10-17 01:00:49 -07:00
Wesley W. Terpstra 73010c79a3 axi4 ToTL: handle bad AXI addresses 2016-10-17 00:12:26 -07:00
Wesley W. Terpstra 501d6d689f axi4: Test ToTL 2016-10-16 22:04:06 -07:00
Wesley W. Terpstra 5a1da63b5a axi4: prototype ToTL adapter 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra 72e5a97d40 tilelink2: factor out the OH1ToOH function 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra d09f43c32f axi4 Bundles: add a size calculation helper 
The old version was wrong.
Inverting before the << has a different width.
This means you end up with high bits set.
 2016-10-16 22:04:01 -07:00
Wesley W. TerpstraandGitHub ee66fd28eb Merge pull request #400 from ucb-bar/better-crossing-asserts 
Better crossing reset handling
 2016-10-14 19:19:37 -07:00
Wesley W. Terpstra 20288729b9 tilelink2 Isolation: cross the valid signals as well 
Refactor the code to be less copy-pasty
 2016-10-14 18:28:36 -07:00
Wesley W. Terpstra 680a944f07 regmapper RegisterCrossing: safe AsyncQueues are overkill here 2016-10-14 18:28:31 -07:00
Wesley W. Terpstra ac0bb841da AsyncQueue: cope with far reset propagation delay 2016-10-14 18:05:35 -07:00
Wesley W. Terpstra 8f3c2ddfc3 tilelink2 Crossing: these asserts should be done by the AsyncQueue 2016-10-14 16:54:09 -07:00
Wesley W. TerpstraandHenry Cook a82cfb8306 tilelink2: replace addr_hi with address (#397) 
When faced with ambiguous routing of wmask=0, we decided to include
all the address bits. Hopefully in most cases the low bits will be
optimized away anyway.
 2016-10-14 14:09:39 -07:00
Wesley W. TerpstraandGitHub 9655621aa8 Merge pull request #396 from ucb-bar/decoupled 
TL2 Decoupled
 2016-10-13 19:09:58 -07:00
Wesley W. Terpstra 4e40f9bb59 tilelink2 Nodes: appease the PC police 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra 54b73aef57 tilelink2: WidthWidget and Fragmenter no longer erase latency 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra 200cf3dd13 tilelink2 Nodes: include some options to test for conformance 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra 5d5b5a66f4 tilelink2 RAMModel: fix a write-bad-data bug 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra e5a1483358 tilelink2 Fragmenter: eliminate most of the registers on A 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra 99c7003d11 tilelink2: allow preemption of Fragmenter and WidthWidget 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra b42cfdc9dd tilelink2 Arbiter: there is only one winner 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra b6e9b0c558 tilelink2 Arbiter: allow preemption of first beat 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra 0aebf9e341 tilelink2 ToAXI4: no arbitration path register needed 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra 0e897b905f tilelink2 RegisterRouter: data path register is no longer required 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra c4eadd3ab3 tilelink2 Monitor: enforce stricter transaction ordering 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra d8a1163131 tilelink2 Monitor: don't enforce Irrevocable any more 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra 405f66da32 tilelink2 WidthWidget: cope with Decoupled inputs 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra e2e72ac979 tilelink2 Fragmenter: cope with Decoupled input 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra 023c6402e9 tilelink2: switch to DecoupledIO syntax 2016-10-13 17:02:17 -07:00
Wesley W. TerpstraandGitHub 980bb3fbfd Merge pull request #395 from ucb-bar/axi4-fragmenter 
AXI4 fragmenter
 2016-10-13 17:01:53 -07:00
Wesley W. Terpstra 4c1c52486b axi4 Fragmenter: handle more inflight AXI requests than we have space 2016-10-13 15:52:32 -07:00
Wesley W. Terpstra 8005266131 axi4 Fragmenter: refine sideband FSM for case of last fragment 2016-10-13 15:52:32 -07:00
Wesley W. Terpstra 19064e602b axi4 Fragmenter: align all output accesses 
We promised the output is aligned. Make good on that!
 2016-10-13 15:52:27 -07:00
Wesley W. Terpstra 84be93f9f3 axi4 Fragmenter: confirm correct handling of last 2016-10-13 14:01:23 -07:00
Wesley W. Terpstra 1c79a23a8b axi4 Fragmenter: initialize error response to 0 2016-10-13 13:46:24 -07:00
Wesley W. Terpstra 958af132ba axi4 Fragmenter: optimize dynamic slave lookup 2016-10-12 17:29:38 -07:00
Wesley W. Terpstra 11169d155c axi4: add a Buffer to put between nodes 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra a9a3f7dd4e tilelink2 RAMModel: include name of test in output 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra 345eefd81b axi4: include unit tests 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra a6c6d99848 axi4: prototype Fragmenter 2016-10-12 17:08:49 -07:00
Wesley W. Terpstra c918aa6d89 axi4: name AdapterNode parameters properly 2016-10-12 17:02:02 -07:00
Wesley W. Terpstra a423f97844 axi4: parameterized AXI master constraint for aligned access 2016-10-12 17:02:02 -07:00
Wesley W. Terpstra 673cf1fdb5 tilelink2 ToAXI4: must create irrevocable D for now 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra 8e92ac32b7 tilelink2 ToAXI4: we need a Queue on B to guarantee deadlock freedom 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra 38b6c1c820 tilelink2 axi4: RegisterRouter can cut ready dependency 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra dc26736f32 axi4 tilelink2: include minAlignment and maxAddress in slaves 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra 538437384a tilelink2 Fragmenter: combine AccessAck errors 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra 4caa543ad7 tilelink2: Fragmenter should not cut Acquire parameters 
The correct response to misuse is to fail a requirement check.
Pretending that things are not caches could lead to inconsistency.
 2016-10-11 22:38:03 -07:00
Wesley W. Terpstra 6336f94fa2 tilelink2: only caches can support B requests 2016-10-11 22:38:02 -07:00
Wesley W. Terpstra 4a975ca380 tilelink2: add a rightOR to go with our leftOR 2016-10-11 22:38:02 -07:00
Wesley W. Terpstra b2a5d18e37 diplomacy: simplify address range fragmentation 2016-10-11 22:36:21 -07:00
Wesley W. TerpstraandGitHub 73e9508c09 Merge pull request #387 from ucb-bar/safer-crossings 
Safer crossings
 2016-10-10 14:44:33 -07:00
Wesley W. Terpstra b0e33f4a39 tilelink2: use TLArbiter in HintHandler 2016-10-10 13:15:28 -07:00
Wesley W. Terpstra 683a2e6785 tilelink2: refactor firstlast helper method 2016-10-10 13:15:28 -07:00