rocketchip: use self-type constraints
This commit is contained in:
Wesley W. Terpstra
parent
d51b0b5c02
commit
5bca13ebdb
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@ -37,7 +37,7 @@ abstract class BareTopModule[+B <: BareTopBundle[BareTop[BaseCoreplex]]](val io:
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}
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/** Base Top with no Periphery */
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trait TopNetwork {
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trait TopNetwork extends HasPeripheryParameters {
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this: BareTop[BaseCoreplex] =>
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implicit val p = q
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TLImp.emitMonitors = p(TLEmitMonitors)
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@ -53,13 +53,13 @@ trait TopNetwork {
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socBus.node))
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}
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trait TopNetworkBundle {
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trait TopNetworkBundle extends HasPeripheryParameters {
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this: BareTopBundle[BareTop[BaseCoreplex]] =>
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implicit val p = outer.q
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val success = Bool(OUTPUT)
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}
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trait TopNetworkModule {
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trait TopNetworkModule extends HasPeripheryParameters {
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this: {
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val outer: BareTop[BaseCoreplex] with TopNetwork
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val io: TopNetworkBundle
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@ -83,10 +83,8 @@ trait HasPeripheryParameters {
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lazy val nMemAXIChannels = if (tMemChannels == BusType.AXI) nMemChannels else 0
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lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0
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lazy val nMemTLChannels = if (tMemChannels == BusType.TL) nMemChannels else 0
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lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
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lazy val edgeSlaveParams = p.alterPartial({ case TLId => "EdgetoSlave" })
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lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" })
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lazy val edgeMMIOParams = p.alterPartial({ case TLId => "MMIOtoEdge" })
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lazy val peripheryBusConfig = p(PeripheryBusKey)
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lazy val socBusConfig = p(SOCBusKey)
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lazy val cacheBlockBytes = p(CacheBlockBytes)
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@ -94,12 +92,14 @@ trait HasPeripheryParameters {
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/////
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trait PeripheryDebug extends LazyModule {
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implicit val p: Parameters
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trait PeripheryDebug {
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this: TopNetwork =>
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}
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trait PeripheryDebugBundle {
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implicit val p: Parameters
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this: TopNetworkBundle {
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val outer: PeripheryDebug
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} =>
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val debug_clk = (p(AsyncDebugBus) && !p(IncludeJtagDTM)).option(Clock(INPUT))
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val debug_rst = (p(AsyncDebugBus) && !p(IncludeJtagDTM)).option(Bool(INPUT))
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val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO()(p).flip)
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@ -107,10 +107,10 @@ trait PeripheryDebugBundle {
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}
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trait PeripheryDebugModule {
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implicit val p: Parameters
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val outer: PeripheryDebug
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val io: PeripheryDebugBundle
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val coreplexDebug: DebugBusIO
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this: TopNetworkModule {
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val outer: PeripheryDebug
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val io: PeripheryDebugBundle
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} =>
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if (p(IncludeJtagDTM)) {
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// JtagDTMWithSync is a wrapper which
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@ -127,9 +127,8 @@ trait PeripheryDebugModule {
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/////
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trait PeripheryExtInterrupts extends LazyModule {
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implicit val p: Parameters
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val intBus: IntXbar
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trait PeripheryExtInterrupts {
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this: TopNetwork =>
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val extInterrupts = IntBlindInputNode(p(NExtTopInterrupts))
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val extInterruptXing = LazyModule(new IntXing)
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@ -139,21 +138,29 @@ trait PeripheryExtInterrupts extends LazyModule {
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}
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trait PeripheryExtInterruptsBundle {
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val outer: PeripheryExtInterrupts
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this: TopNetworkBundle {
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val outer: PeripheryExtInterrupts
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} =>
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val interrupts = outer.extInterrupts.bundleIn
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}
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trait PeripheryExtInterruptsModule {
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this: TopNetworkModule {
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val outer: PeripheryExtInterrupts
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val io: PeripheryExtInterruptsBundle
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} =>
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}
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/////
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trait PeripheryMasterMem extends LazyModule {
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implicit val p: Parameters
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trait PeripheryMasterMem {
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this: TopNetwork =>
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}
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trait PeripheryMasterMemBundle extends HasPeripheryParameters {
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implicit val p: Parameters
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trait PeripheryMasterMemBundle {
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this: TopNetworkBundle {
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val outer: PeripheryMasterMem
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} =>
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val mem_clk = p(AsyncMemChannels).option(Vec(nMemChannels, Clock(INPUT)))
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val mem_rst = p(AsyncMemChannels).option(Vec(nMemChannels, Bool (INPUT)))
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val mem_axi = Vec(nMemAXIChannels, new NastiIO)
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@ -161,11 +168,11 @@ trait PeripheryMasterMemBundle extends HasPeripheryParameters {
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val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(edgeMemParams))
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}
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trait PeripheryMasterMemModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val outer: PeripheryMasterMem
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val io: PeripheryMasterMemBundle
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val coreplexMem: Vec[ClientUncachedTileLinkIO]
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trait PeripheryMasterMemModule {
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this: TopNetworkModule {
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val outer: PeripheryMasterMem
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val io: PeripheryMasterMemBundle
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} =>
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val edgeMem = coreplexMem.map(TileLinkWidthAdapter(_, edgeMemParams))
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@ -192,9 +199,8 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
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/////
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// PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one.
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trait PeripheryMasterAXI4MMIO extends HasPeripheryParameters {
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implicit val p: Parameters
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val socBus: TLXbar
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trait PeripheryMasterAXI4MMIO {
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this: TopNetwork =>
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val mmio_axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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@ -212,40 +218,45 @@ trait PeripheryMasterAXI4MMIO extends HasPeripheryParameters {
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socBus.node))
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}
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trait PeripheryMasterAXI4MMIOBundle extends HasPeripheryParameters {
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val outer: PeripheryMasterAXI4MMIO
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trait PeripheryMasterAXI4MMIOBundle {
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this: TopNetworkBundle {
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val outer: PeripheryMasterAXI4MMIO
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} =>
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val mmio_axi = outer.mmio_axi4.bundleOut
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}
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trait PeripheryMasterAXI4MMIOModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val outer: PeripheryMasterAXI4MMIO
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val io: PeripheryMasterAXI4MMIOBundle
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trait PeripheryMasterAXI4MMIOModule {
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this: TopNetworkModule {
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val outer: PeripheryMasterAXI4MMIO
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val io: PeripheryMasterAXI4MMIOBundle
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} =>
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// nothing to do
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}
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/////
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trait PeripherySlave extends LazyModule {
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implicit val p: Parameters
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val pBusMasters: RangeManager
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trait PeripherySlave {
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this: TopNetwork {
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val pBusMasters: RangeManager
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} =>
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if (p(NExtBusAXIChannels) > 0) pBusMasters.add("ext", 1) // NExtBusAXIChannels are arbitrated into one TL port
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}
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trait PeripherySlaveBundle extends HasPeripheryParameters {
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implicit val p: Parameters
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trait PeripherySlaveBundle {
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this: TopNetworkBundle {
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val outer: PeripherySlave
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} =>
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val bus_clk = p(AsyncBusChannels).option(Vec(p(NExtBusAXIChannels), Clock(INPUT)))
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val bus_rst = p(AsyncBusChannels).option(Vec(p(NExtBusAXIChannels), Bool (INPUT)))
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val bus_axi = Vec(p(NExtBusAXIChannels), new NastiIO).flip
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}
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trait PeripherySlaveModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val outer: PeripherySlave
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val io: PeripherySlaveBundle
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val coreplexSlave: Vec[ClientUncachedTileLinkIO]
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trait PeripherySlaveModule {
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this: TopNetworkModule {
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val outer: PeripherySlave { val pBusMasters: RangeManager }
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val io: PeripherySlaveBundle
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} =>
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if (p(NExtBusAXIChannels) > 0) {
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val arb = Module(new NastiArbiter(p(NExtBusAXIChannels)))
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@ -266,72 +277,76 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
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/////
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trait PeripheryBootROM extends LazyModule with HasPeripheryParameters {
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implicit val p: Parameters
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val peripheryBus: TLXbar
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trait PeripheryBootROM {
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this: TopNetwork =>
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val address = 0x1000
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val size = 0x1000
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val bootrom = LazyModule(new TLROM(address, size, GenerateBootROM(p, address), true, peripheryBusConfig.beatBytes))
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val bootrom_address = 0x1000
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val bootrom_size = 0x1000
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val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, GenerateBootROM(p, bootrom_address), true, peripheryBusConfig.beatBytes))
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bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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}
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trait PeripheryBootROMBundle {
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implicit val p: Parameters
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this: TopNetworkBundle {
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val outer: PeripheryBootROM
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} =>
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}
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trait PeripheryBootROMModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val outer: PeripheryBootROM
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val io: PeripheryBootROMBundle
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trait PeripheryBootROMModule {
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this: TopNetworkModule {
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val outer: PeripheryBootROM
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val io: PeripheryBootROMBundle
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} =>
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}
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/////
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trait PeripheryTestRAM extends LazyModule with HasPeripheryParameters {
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implicit val p: Parameters
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val peripheryBus: TLXbar
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trait PeripheryTestRAM {
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this: TopNetwork =>
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val ramBase = 0x52000000
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val ramSize = 0x1000
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val sram = LazyModule(new TLRAM(AddressSet(ramBase, ramSize-1), true, peripheryBusConfig.beatBytes)
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{ override def name = "testram" })
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sram.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, peripheryBusConfig.beatBytes))
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testram.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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}
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trait PeripheryTestRAMBundle {
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implicit val p: Parameters
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this: TopNetworkBundle {
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val outer: PeripheryTestRAM
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} =>
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}
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trait PeripheryTestRAMModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val outer: PeripheryTestRAM
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trait PeripheryTestRAMModule {
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this: TopNetworkModule {
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val outer: PeripheryTestRAM
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val io: PeripheryTestRAMBundle
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} =>
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}
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/////
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trait PeripheryTestBusMaster extends LazyModule {
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implicit val p: Parameters
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val peripheryBus: TLXbar
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trait PeripheryTestBusMaster {
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this: TopNetwork =>
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val fuzzer = LazyModule(new TLFuzzer(5000))
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peripheryBus.node := fuzzer.node
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}
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trait PeripheryTestBusMasterBundle {
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implicit val p: Parameters
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this: TopNetworkBundle {
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val outer: PeripheryTestBusMaster
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} =>
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}
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trait PeripheryTestBusMasterModule {
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implicit val p: Parameters
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val outer: PeripheryTestBusMaster
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this: TopNetworkModule {
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val outer: PeripheryTestBusMaster
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val io: PeripheryTestBusMasterBundle
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} =>
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}
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/////
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trait HardwiredResetVector {
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val outer: BaseTop[BaseCoreplex]
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this: TopNetworkModule {
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val outer: BaseTop[BaseCoreplex]
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} =>
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outer.coreplex.module.io.resetVector := UInt(0x1000) // boot ROM
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}
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