coreplex: use self-type constraints
This commit is contained in:
Wesley W. Terpstra
parent
ac886026e6
commit
6505431eac
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@ -48,36 +48,89 @@ trait HasCoreplexParameters {
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case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters
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abstract class BareCoreplex(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters {
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abstract class BareCoreplex(implicit val p: Parameters) extends LazyModule
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abstract class BareCoreplexBundle[+L <: BareCoreplex](val outer: L) extends Bundle
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abstract class BareCoreplexModule[+B <: BareCoreplexBundle[BareCoreplex]](val io: B) extends LazyModuleImp(io.outer) {
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val outer = io.outer.asInstanceOf[io.outer.type]
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}
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trait CoreplexNetwork extends HasCoreplexParameters {
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this: BareCoreplex =>
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val l1tol2 = LazyModule(new TLXbar)
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val mmio = TLOutputNode()
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val l1tol2_beatBytes = p(rocketchip.EdgeDataBits)/8
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val l1tol2_lineBytes = p(CacheBlockBytes)
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val cbus = LazyModule(new TLXbar)
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val cbus_beatBytes = p(XLen)/8
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val cbus_lineBytes = l1tol2_lineBytes
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cbus.node :=
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TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
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TLWidthWidget(l1tol2_beatBytes)(
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TLBuffer()(
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l1tol2.node)))
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}
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trait CoreplexNetworkBundle extends HasCoreplexParameters {
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this: BareCoreplexBundle[BareCoreplex] =>
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implicit val p = outer.p
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}
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trait CoreplexNetworkModule extends HasCoreplexParameters {
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this: BareCoreplexModule[BareCoreplexBundle[BareCoreplex]] =>
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implicit val p = outer.p
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}
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trait CoreplexRISCV {
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this: CoreplexNetwork =>
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// Build a set of Tiles
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val lazyTiles = p(BuildTiles) map { _(p) }
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val legacy = LazyModule(new TLLegacy()(outerMMIOParams))
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mmio :=
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TLBuffer()(
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TLWidthWidget(legacy.tlDataBytes)(
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l1tol2.node))
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val debug = LazyModule(new TLDebugModule())
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val plic = LazyModule(new TLPLIC(() => plicKey))
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val clint = LazyModule(new CoreplexLocalInterrupter(clintKey))
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val mmio = TLOutputNode()
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// Kill this once we move TL2 into rocket
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l1tol2.node :=
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TLHintHandler()(
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legacy.node)
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debug.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
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plic.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
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clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
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mmio :=
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TLBuffer()(
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TLWidthWidget(l1tol2_beatBytes)(
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l1tol2.node))
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}
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abstract class BareCoreplexBundle[+L <: BareCoreplex](val outer: L) extends Bundle with HasCoreplexParameters {
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implicit val p = outer.p
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trait CoreplexRISCVBundle {
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this: CoreplexNetworkBundle {
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val outer: CoreplexRISCV
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} =>
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
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val mmio = outer.mmio.bundleOut
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
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val slave = Vec(nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
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val resetVector = UInt(INPUT, p(XLen))
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val success = Bool(OUTPUT) // used for testing
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val debug = new DebugBusIO().flip
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val interrupts = Vec(nExtInterrupts, Bool()).asInput
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}
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abstract class BareCoreplexModule[+B <: BareCoreplexBundle[BareCoreplex]](val io: B) extends LazyModuleImp(io.outer) with HasCoreplexParameters {
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val outer = io.outer.asInstanceOf[io.outer.type]
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implicit val p = outer.p
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trait CoreplexRISCVModule {
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this: CoreplexNetworkModule {
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val outer: CoreplexNetwork with CoreplexRISCV
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val io: CoreplexRISCVBundle
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} =>
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val tiles = outer.lazyTiles.map(_.module)
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val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) }
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// Create and export the ConfigString
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val managers = outer.l1tol2.node.edgesIn(0).manager.managers
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@ -85,14 +138,10 @@ abstract class BareCoreplexModule[+B <: BareCoreplexBundle[BareCoreplex]](val io
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println(s"\nGenerated Configuration String\n${configString}")
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ConfigStringOutput.contents = Some(configString)
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// Build a set of Tiles
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val tiles = outer.lazyTiles.map(_.module)
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val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) }
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val nCachedPorts = tiles.map(tile => tile.io.cached.size).reduce(_ + _)
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val nUncachedPorts = tiles.map(tile => tile.io.uncached.size).reduce(_ + _)
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val nBanks = nMemChannels * nBanksPerMemChannel
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buildUncore(p.alterPartial({
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case HastiId => "TL"
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case TLId => "L1toL2"
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@ -139,48 +188,18 @@ abstract class BareCoreplexModule[+B <: BareCoreplexBundle[BareCoreplex]](val io
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io.mem <> mem_ic.io.out
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}
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// connect coreplex-internal interrupts to tiles
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for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
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tile.hartid := UInt(i)
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tile.resetVector := io.resetVector
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tile.interrupts <> outer.clint.module.io.tiles(i)
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tile.interrupts.meip := outer.plic.module.io.harts(plicKey.context(i, 'M'))
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tile.interrupts.seip.foreach(_ := outer.plic.module.io.harts(plicKey.context(i, 'S')))
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tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
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}
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// Coreplex doesn't know when to stop running
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io.success := Bool(false)
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}
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trait CoreplexPeripherals extends HasCoreplexParameters {
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val module: CoreplexPeripheralsModule
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val l1tol2: TLXbar
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val legacy: TLLegacy
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val cbus = LazyModule(new TLXbar)
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val debug = LazyModule(new TLDebugModule())
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val plic = LazyModule(new TLPLIC(() => plicKey))
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val clint = LazyModule(new CoreplexLocalInterrupter(clintKey))
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cbus.node :=
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TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
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TLWidthWidget(legacy.tlDataBytes)(
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TLBuffer()(
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l1tol2.node)))
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debug.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
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plic.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
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clint.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
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}
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trait CoreplexPeripheralsBundle extends HasCoreplexParameters {
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val outer: CoreplexPeripherals
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val debug = new DebugBusIO().flip
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val interrupts = Vec(nExtInterrupts, Bool()).asInput
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}
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trait CoreplexPeripheralsModule extends HasCoreplexParameters {
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val outer: CoreplexPeripherals
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val io: CoreplexPeripheralsBundle
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val uncoreTileIOs: Seq[TileIO]
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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@ -189,23 +208,18 @@ trait CoreplexPeripheralsModule extends HasCoreplexParameters {
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outer.debug.module.io.db <> io.debug
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outer.clint.module.io.rtcTick := Counter(p(rocketchip.RTCPeriod)).inc()
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// connect coreplex-internal interrupts to tiles
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for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
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tile.interrupts <> outer.clint.module.io.tiles(i)
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tile.interrupts.meip := outer.plic.module.io.harts(plicKey.context(i, 'M'))
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tile.interrupts.seip.foreach(_ := outer.plic.module.io.harts(plicKey.context(i, 'S')))
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tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
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}
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}
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class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
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with CoreplexPeripherals {
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with CoreplexNetwork
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with CoreplexRISCV {
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override lazy val module = new BaseCoreplexModule(new BaseCoreplexBundle(this))
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}
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class BaseCoreplexBundle[+L <: BaseCoreplex](outer: L) extends BareCoreplexBundle(outer)
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with CoreplexPeripheralsBundle
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with CoreplexNetworkBundle
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with CoreplexRISCVBundle
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class BaseCoreplexModule[+B <: BaseCoreplexBundle[BaseCoreplex]](io: B) extends BareCoreplexModule(io)
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with CoreplexPeripheralsModule
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with CoreplexNetworkModule
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with CoreplexRISCVModule
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@ -11,17 +11,12 @@ import util._
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import rocket._
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trait DirectConnection {
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implicit val p: Parameters
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val lazyTiles: Seq[LazyTile]
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val legacy: TLLegacy
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val cbus: TLXbar
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this: CoreplexNetwork with CoreplexRISCV =>
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lazyTiles.map(_.slave).flatten.foreach { scratch => scratch := cbus.node }
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}
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trait DirectConnectionModule {
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val tiles: Seq[TileImp]
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val uncoreTileIOs: Seq[TileIO]
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this: CoreplexNetworkModule with CoreplexRISCVModule =>
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val tlBuffering = TileLinkDepths(1,1,2,2,0)
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val ultBuffering = UncachedTileLinkDepths(1,2)
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@ -49,19 +44,8 @@ class DefaultCoreplexModule[+B <: DefaultCoreplexBundle[DefaultCoreplex]](io: B)
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/////
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trait TileClockResetBundle extends Bundle with HasCoreplexParameters {
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val tcrs = Vec(nTiles, new Bundle {
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val clock = Clock(INPUT)
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val reset = Bool(INPUT)
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})
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}
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trait AsyncConnection {
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implicit val p: Parameters
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val lazyTiles: Seq[LazyTile]
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val legacy: TLLegacy
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val cbus: TLXbar
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this: CoreplexNetwork with CoreplexRISCV =>
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val crossings = lazyTiles.map(_.slave).map(_.map { scratch =>
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val crossing = LazyModule(new TLAsyncCrossing)
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crossing.node := cbus.node
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@ -70,11 +54,19 @@ trait AsyncConnection {
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})
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}
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trait AsyncConnectionModule extends Module {
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val io: TileClockResetBundle
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val tiles: Seq[TileImp]
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val uncoreTileIOs: Seq[TileIO]
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val outer: AsyncConnection
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trait AsyncConnectionBundle {
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this: CoreplexNetworkBundle with CoreplexRISCVBundle =>
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val tcrs = Vec(nTiles, new Bundle {
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val clock = Clock(INPUT)
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val reset = Bool(INPUT)
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})
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}
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trait AsyncConnectionModule {
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this: Module with CoreplexNetworkModule with CoreplexRISCVModule {
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val outer: AsyncConnection
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val io: AsyncConnectionBundle
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} =>
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(outer.crossings zip io.tcrs) foreach { case (slaves, tcr) =>
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slaves.foreach { case (crossing, monitor) =>
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@ -115,7 +107,7 @@ class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex
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}
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class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](outer: L) extends BaseCoreplexBundle(outer)
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with TileClockResetBundle
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with AsyncConnectionBundle
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class MultiClockCoreplexModule[+B <: MultiClockCoreplexBundle[MultiClockCoreplex]](io: B) extends BaseCoreplexModule(io)
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with AsyncConnectionModule
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