riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2: only caches can support B requests

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-10-10 11:45:43 -07:00
parent 4a975ca380
commit 6336f94fa2
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/main/scala/uncore/tilelink2/Parameters.scala
View File

@ -166,6 +166,13 @@ case class TLClientParameters(
supportsHint: TransferSizes = TransferSizes.none)
{
require (supportsPutFull.contains(supportsPutPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supportsProbe.contains(supportsArithmetic))
require (supportsProbe.contains(supportsLogical))
require (supportsProbe.contains(supportsGet))
require (supportsProbe.contains(supportsPutFull))
require (supportsProbe.contains(supportsPutPartial))
require (supportsProbe.contains(supportsHint))
val maxTransfer = List(
supportsProbe.max,