Andrew Waterman
ff8c736d94
move icache invalidate out of request bundle
2012-11-16 01:55:45 -08:00
Yunsup Lee
be1980dd2d
refactored vector queue interface
2012-11-07 01:15:33 -08:00
Andrew Waterman
4d1ca8ba3a
remove more global consts; refactor DTLBs
...
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
2012-11-06 08:13:44 -08:00
Andrew Waterman
e76892f758
remove more global constants
2012-11-06 02:55:45 -08:00
Andrew Waterman
c5b93798fb
factor out more global constants
2012-11-05 23:52:32 -08:00
Andrew Waterman
5b20ed71be
move rd=0 check into bypass logic
...
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
2012-11-05 01:30:57 -08:00
Andrew Waterman
7380c9fe60
aggressively clock gate int and fp datapaths
2012-11-04 16:40:14 -08:00
Henry Cook
88ac5af181
Merged consts-as-traits
2012-10-16 16:32:35 -07:00
Andrew Waterman
197154c485
use BTB for JALR
2012-10-16 02:24:37 -07:00
Andrew Waterman
661f8e635b
merge I$, ITLB, BTB into Frontend
2012-10-16 02:24:37 -07:00
Henry Cook
dfdfddebe8
constants as traits
2012-10-07 22:20:03 -07:00
Henry Cook
b5ff436092
decode constant object split into multiple objects
2012-10-05 15:50:42 -07:00
Andrew Waterman
4e44ed7400
allow back pressure on IPI requests
2012-07-17 22:55:40 -07:00
Huy Vo
fd95159837
INPUT/OUTPUT orderring swapped
2012-07-12 18:16:57 -07:00
Huy Vo
c975c21e44
views removed
2012-06-06 12:51:26 -07:00
Huy Vo
7408c9ab69
removing wires
2012-05-24 10:42:39 -07:00
Andrew Waterman
faee45bf4c
fix setpcr/clearpcr not writing rd
2012-05-21 07:25:35 -07:00
Gage W Eads
d0bc995c88
Fixed IRQ_IPI -> IRQ_TIMER typo
2012-05-14 22:25:12 -07:00
Henry Cook
622a801bb1
Refactored cpu/cache interface to use nested bundles
2012-05-02 11:54:28 -07:00
Andrew Waterman
65ff397122
improved instruction decoding
...
it now makes use of don't-cares by performing logic minimization
2012-05-01 20:16:36 -07:00
Huy Vo
c9c3bd02bc
kill mem stage if fpu nacks in mem stage
2012-04-01 17:02:32 -07:00
Andrew Waterman
7f254d9670
refine FP bugfixes
2012-04-01 14:52:33 -07:00
Huy Vo
c7c35322c2
two bug fixes to fpu
2012-03-31 22:23:51 -07:00
Andrew Waterman
452876af37
fence on vvcfg; implement fence.v.g correctly
2012-03-27 14:49:00 -07:00
Andrew Waterman
54fa6f660d
new supervisor mode
2012-03-24 13:03:31 -07:00
Yunsup Lee
aaed0241af
get rid of vxcptwait
2012-03-21 15:09:04 -07:00
Yunsup Lee
023734175d
now fence stalls in decode
2012-03-20 17:10:05 -07:00
Yunsup Lee
e450e3aa40
fix irt counter bug regarding vector stuff
2012-03-20 17:09:54 -07:00
Yunsup Lee
c036fff79c
fix id interrupt signal
2012-03-19 15:13:57 -07:00
Yunsup Lee
264732556f
fixes to match verilog X semantics
2012-03-19 03:10:00 -07:00
Andrew Waterman
bd27d0fab2
can now take interrupts on stalled instructions
2012-03-19 01:02:06 -07:00
Andrew Waterman
c4a91303fb
update vector fence names and encoding
2012-03-18 20:42:38 -07:00
Yunsup Lee
b793d63182
no vector interrupt masking
2012-03-17 23:01:06 -07:00
Yunsup Lee
b19d783fbd
add vector irq handler
2012-03-14 14:15:28 -07:00
Yunsup Lee
040d62f372
refactored vector exception handling interface
2012-03-13 23:45:34 -07:00
Yunsup Lee
5655dbd5da
add vvcfg and vtcfg instructions
2012-03-13 23:45:34 -07:00
Yunsup Lee
1ba5e7b865
changes to the vector exception interface
2012-03-11 21:38:47 -07:00
Yunsup Lee
e42a4c767e
don't stall on vector fences, keep replaying
2012-03-11 16:29:19 -07:00
Yunsup Lee
44ff22a26f
vector exception handler now handles prefetches correctly
2012-03-10 12:54:36 -08:00
Andrew Waterman
85504f0ddc
fix bug in fence.i and improve test
2012-03-09 03:26:05 -08:00
Yunsup Lee
8acbe98f53
change how fence.*.cv works, now control processor stalls on the fence instruction
2012-03-08 23:32:31 -08:00
Yunsup Lee
e28a551368
refactor code related to vector exceptions
...
- revisied interfaces
- new instructions
2012-03-03 15:15:00 -08:00
Yunsup Lee
8678b3d70c
clean up ioDecoupled/ioPipe interface
2012-03-01 20:48:46 -08:00
Yunsup Lee
c7b01230f4
fix mul/div when waddr=0, can't believe torture didn't find this one
2012-03-01 10:15:27 -08:00
Andrew Waterman
e12b9eae93
remove ext_mem interface
...
hindsight is 20/20
2012-02-26 18:53:39 -08:00
Yunsup Lee
94ba32bbd3
change package name and sbt project name to rocket
2012-02-25 17:09:26 -08:00
Yunsup Lee
a1600d95db
fix bug related to waddr and wdata in wb stage
...
for the instructions which don't use waddr/wdata for writeback, the contents were getting overwritten by the ll ops
it manifested itself after cp imul were sharing the alu with the vu
2012-02-25 12:21:10 -08:00
Yunsup Lee
137fd62007
refactor cpfences
2012-02-25 12:20:36 -08:00
Andrew Waterman
4121fb178c
clean up mul/div interface; use VU mul if HAVE_VEC
2012-02-24 19:22:35 -08:00
Andrew Waterman
b3a3289d34
fix (?) external memory request nack interface
2012-02-24 01:42:33 -08:00
Yunsup Lee
63939efd0c
fix ctrl vec iface hookup - final
2012-02-23 23:03:44 -08:00
Yunsup Lee
bf1e643913
fix ctrl vec iface hookup
2012-02-23 22:55:25 -08:00
Andrew Waterman
6ceaa0e80a
correct and simplify replay_next logic
2012-02-23 16:52:52 -08:00
Andrew Waterman
f939088be1
move datapath control signals into control unit
...
because that's where control signals go
2012-02-23 16:52:52 -08:00
Andrew Waterman
7c929afe2b
HTIF now controls CPU reset
2012-02-22 19:30:03 -08:00
Andrew Waterman
7034c9be65
new htif protocol and implementation
...
You must update your fesvr and isasim!
2012-02-19 23:15:45 -08:00
Andrew Waterman
8b3b3abd3d
fix external memory request nack logic
2012-02-15 18:57:40 -08:00
Andrew Waterman
fe2c1d1321
add vec->ctrl fences
2012-02-15 18:31:19 -08:00
Yunsup Lee
82cd3625c2
add in vackq interface
2012-02-15 17:53:24 -08:00
Andrew Waterman
c13524ad3a
fix vcmdq full replay logic
2012-02-15 17:49:12 -08:00
Yunsup Lee
258d050e1b
add stall logic for vector command queues
2012-02-15 14:48:41 -08:00
Yunsup Lee
32bdf5098a
refactor vector control logic & datapath in the rocket core
2012-02-15 13:30:22 -08:00
Yunsup Lee
7c11c1406c
vector-vector add working!
2012-02-15 02:28:07 -08:00
Andrew Waterman
0ec7767c13
declaring success on FPU for now
2012-02-14 19:11:57 -08:00
Andrew Waterman
297223a13c
squash subsequent external mem request after nack
2012-02-14 15:12:16 -08:00
Andrew Waterman
15dc2d8c40
add fp writeback arbitration logic
2012-02-14 00:32:25 -08:00
Andrew Waterman
0366465cb1
parameterize the scoreboards
2012-02-13 18:12:23 -08:00
Andrew Waterman
c78c738f60
minor cleanups
2012-02-13 03:13:49 -08:00
Andrew Waterman
a4a9d2312c
add fcvt.[w|l][u].[s|d], f[eq|lt|le].[s|d]
2012-02-13 01:30:01 -08:00
Andrew Waterman
08b6517a23
add FP ops mftx, mxtf, mtfsr, mffsr
2012-02-12 20:12:53 -08:00
Andrew Waterman
9bb1558a34
WIP on FPU
2012-02-12 04:36:01 -08:00
Andrew Waterman
50a283d311
move store data generation into EX stage
...
doing so removes it from the critical path of FP store unrecoding.
2012-02-12 01:35:55 -08:00
Andrew Waterman
725190d0ee
update to new chisel
2012-02-11 17:20:33 -08:00
Yunsup Lee
f47d888feb
vvcfgivl and vsetvl works
2012-02-09 02:35:21 -08:00
Andrew Waterman
128ec567ed
make BTB fully associative; don't use it for JALR
...
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
2012-02-09 01:34:00 -08:00
Yunsup Lee
fcc8081c4d
hook up the vector command queue
2012-02-09 01:28:16 -08:00
Andrew Waterman
8b6b0f5367
add external memory request interface for vec unit
2012-02-08 22:30:45 -08:00
Yunsup Lee
9285a52f25
initial vu integration
2012-02-08 21:43:45 -08:00
Andrew Waterman
10b5a0006c
fix mul/div to rd=0
2012-02-08 20:11:57 -08:00
Andrew Waterman
e9da2cf66a
improve id/ex datapath
...
move operand selection into decode stage; simplify bypassing
2012-02-08 06:47:26 -08:00
Andrew Waterman
d471a8b2da
arbitrate for LLFU writebacks in MEM stage
2012-02-08 04:21:05 -08:00
Andrew Waterman
ebed56500e
fix mul/wb hazard checks
...
I erroneously assumed that those instructions set id_wen.
2012-02-08 01:56:11 -08:00
Andrew Waterman
5403d069e9
add fp loads/stores
2012-02-07 23:54:25 -08:00
Andrew Waterman
fde8e3b696
clean up bypassing/hazard checking a bit
2012-02-06 17:26:45 -08:00
Andrew Waterman
38c9105ea1
fix mul/div deadlock bug
...
If independent multiplies or independent divides were issued
back-to-back, the second wouldn't execute, causing the register
to be busy forever.
2012-01-30 21:14:28 -08:00
Andrew Waterman
bd241ea237
fix when badvaddr is set
2012-01-30 17:15:42 -08:00
Andrew Waterman
a96c92f58d
enable amomin[u]/amomax[u
2012-01-26 20:45:04 -08:00
Andrew Waterman
a7999d4525
don't flush I$ unless fence.i commits
...
otherwise, we might not make forward progress.
2012-01-26 20:37:09 -08:00
Andrew Waterman
7172ddd050
don't flush pipeline after MFPCR
2012-01-24 18:40:08 -08:00
Andrew Waterman
9e6b86fe85
Fix a nasty replay bug
...
If a mispredicted branch was followed by an instruction dependent
on a load that missed in the cache, the mispredicted path would
be executed rather than the correct path. Fail.
Example broken code:
lw x2, 0(x2) # cache miss
beq x3, x0, somewhere # mispredicted branch
move x4, x2 # wrong-path instruction dependent on load miss
2012-01-24 03:40:01 -08:00
Andrew Waterman
06fdf79dab
fix long-latency writeback arbitration bug
2012-01-24 00:56:47 -08:00
Andrew Waterman
d59bddfbf1
fix I$ miss replay bug
2012-01-21 20:42:13 -08:00
Henry Cook
1d76255dc1
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 14:39:57 -08:00
Andrew Waterman
e4cf6391d7
fix i$ miss pathology and badvaddr bug
2012-01-17 23:47:35 -08:00
Andrew Waterman
0369b05deb
move replays to writeback stage
2012-01-17 21:12:31 -08:00
Andrew Waterman
1c8f496811
fix fpga build
2012-01-13 20:04:11 -08:00
Andrew Waterman
acf3134e80
minor control logic cleanup
2012-01-12 14:19:18 -08:00
Andrew Waterman
4807d7222b
use replay to handle I$ misses
...
this eliminates a long path in the fetch stage
2012-01-11 19:20:20 -08:00
Andrew Waterman
1a7bfd4350
remove icache req_rdy signal
2012-01-11 18:27:11 -08:00
Andrew Waterman
bcb55e581a
remove host.start signal, use reset instead
2012-01-11 17:49:32 -08:00