Henry Cook
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c03976896e
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separate queues for resp tag and data
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2015-03-15 17:58:17 -07:00 |
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Andrew Waterman
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6e540825b2
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Use entire 12-bit CSR address
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2015-03-14 02:15:24 -07:00 |
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Yunsup Lee
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3a78ca210d
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bugfix in uncached TL to TL convertors
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2015-03-12 16:33:41 -07:00 |
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Henry Cook
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8181262419
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clean up incoherent and probe flags
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2015-03-12 16:22:14 -07:00 |
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Henry Cook
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dcc84c4dd3
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arbiter probe ready bugfix
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2015-03-12 16:02:51 -07:00 |
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Yunsup Lee
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2c31ed6426
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previous bug fix for meta data writeback wasn't quite right
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2015-03-12 15:34:20 -07:00 |
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Yunsup Lee
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5e40c8ba77
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write back meta data when cache miss even when coherence meta data is clean
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2015-03-12 14:36:46 -07:00 |
|
Albert Ou
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8f8022379c
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Fix AMO opcode extraction
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2015-03-11 23:24:58 -07:00 |
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Albert Ou
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f75126c39c
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Require self probes for all built-in Acquire types
This ensures that puts by the RoCC accelerator properly invalidates its
tile's L1 D$, with which it currently shares the same TileLink port.
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2015-03-11 23:24:58 -07:00 |
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Henry Cook
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1aff919c24
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added prefetchAck Grant type
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2015-03-11 17:32:06 -07:00 |
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Henry Cook
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059575c334
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cleanup mergeData and prep for cleaner data_buffer in L2
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2015-03-11 15:43:41 -07:00 |
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Henry Cook
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b4ed1d9121
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Add builtin prefetch types to TileLink
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2015-03-11 14:28:17 -07:00 |
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Yunsup Lee
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3ab1aca7de
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L2 subblock access bugfix
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2015-03-11 01:56:47 -07:00 |
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Henry Cook
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17072a0041
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L2 Writeback bugfix
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2015-03-10 01:15:03 -07:00 |
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Henry Cook
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a1f04386f7
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Headerless TileLinkIO and arbiters
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2015-03-09 16:34:59 -07:00 |
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Henry Cook
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002f1a1b39
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pin outer finish header
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2015-03-09 12:40:37 -07:00 |
|
Henry Cook
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df79e7ff8d
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secondary miss bug
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2015-03-05 15:51:18 -08:00 |
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Henry Cook
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8e41fcf6fc
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reduce MemIFTag size, enable non pow2 HellaFLowQueue size
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2015-03-05 15:51:02 -08:00 |
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Henry Cook
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1bed6ea498
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New metadata-based coherence API
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2015-02-28 17:32:03 -08:00 |
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Henry Cook
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0a8722e881
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bugfix for indexing DataArray of of small L2
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2015-02-17 00:37:40 -08:00 |
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Henry Cook
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0c66e70f14
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cleanup of conflicts; allocation bugfix
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2015-02-06 13:20:44 -08:00 |
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Henry Cook
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7b86ea17cf
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rename L2HellaCache to L2HellaCacheBank
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2015-02-03 19:38:01 -08:00 |
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Stephen Twigg
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3b3250339a
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Explicitely convert results of Bits Muxes to UInt
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
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2015-02-03 18:15:01 -08:00 |
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Henry Cook
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57340be72b
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doc update
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2015-02-02 01:11:13 -08:00 |
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Henry Cook
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6141b3efc5
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uncached -> builtin_type
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2015-02-02 01:02:06 -08:00 |
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Henry Cook
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e6491d351f
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Offset AMOs within beat and return old value
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2015-02-02 00:22:21 -08:00 |
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Henry Cook
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3aa030f960
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Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor.
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2015-02-01 20:37:16 -08:00 |
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Henry Cook
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7b4e9dd137
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Block L2 transactions on the same set from proceeding in parallel
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2015-02-01 20:29:23 -08:00 |
|
Henry Cook
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973eb43128
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state machine bug on uncached write hits
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2015-02-01 20:29:23 -08:00 |
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Henry Cook
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f58f8bf385
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Make L2 data array use a single Mem
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2015-01-25 15:37:04 -08:00 |
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Henry Cook
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9ef00d187f
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%s/master/manager/g + better comments
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2014-12-29 22:55:58 -08:00 |
|
Henry Cook
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c76b4bc21d
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TileLink doc
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2014-12-29 22:55:18 -08:00 |
|
Henry Cook
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e62c71203e
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disconnect unused outer network headers
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2014-12-22 18:50:37 -08:00 |
|
Henry Cook
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2ef4357ca8
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acquire allocation bugfix
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2014-12-19 17:39:23 -08:00 |
|
Henry Cook
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f234fe65ce
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Initial verison of L2WritebackUnit, passes MiT2 bmark tests
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2014-12-19 03:03:53 -08:00 |
|
Henry Cook
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d121af7f94
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Simplify release handling
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2014-12-18 17:12:29 -08:00 |
|
Henry Cook
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bfcfc3fe18
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refactor cache params
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2014-12-17 14:28:14 -08:00 |
|
Henry Cook
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ab39cbb15d
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cleanup DirectoryRepresentation and coherence params
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2014-12-15 19:24:42 -08:00 |
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Andrew Waterman
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d04da83f96
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Make data RAMs 1RW instead of 1R1W
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2014-12-15 17:36:17 -08:00 |
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Henry Cook
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6a8b66231c
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Add uncached->cached tilelink converter
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2014-12-12 17:06:03 -08:00 |
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Henry Cook
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424df2368f
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1R/W L2 data array?
Add TLDataBeats to new LLC; all bmarks pass
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2014-12-12 17:05:21 -08:00 |
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Henry Cook
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3026c46a9c
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Finish adding TLDataBeats to uncore & hub
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2014-12-12 17:04:52 -08:00 |
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Henry Cook
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2f733a60db
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Begin adding TLDataBeats to uncore
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2014-12-12 17:04:31 -08:00 |
|
Henry Cook
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404773eb9f
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fix wb bug
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2014-12-03 14:22:39 -08:00 |
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Henry Cook
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05b5188ad9
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meta and data bundle refactor
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2014-11-19 15:55:25 -08:00 |
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Henry Cook
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a519a43f23
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Merge branch 'master' into new-llc
Conflicts:
src/main/scala/coherence.scala
src/main/scala/memserdes.scala
src/main/scala/tilelink.scala
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2014-11-12 16:25:25 -08:00 |
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Henry Cook
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cb7e712599
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Added uncached write data queue to coherence hub
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2014-11-12 12:55:07 -08:00 |
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Henry Cook
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82155f333e
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Major tilelink revision for uncached message types
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2014-11-11 17:36:55 -08:00 |
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Henry Cook
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35553cc0b7
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NullDirectory sharers.count fix
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2014-11-11 16:05:25 -08:00 |
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Henry Cook
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10309849b7
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Remove master_xact_id from Probe and Release
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2014-11-06 12:07:33 -08:00 |
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