Howard Mao
82169e971e
Dynamically compute number of L1 client channels
...
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.
This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
2016-06-20 13:02:31 -07:00
Wesley W. Terpstra
70d92995df
TestConfigs: add comparator config
2016-06-09 15:43:13 -07:00
Howard Mao
1679cf4764
fix groundtest tilelink xacts
2016-06-09 15:42:44 -07:00
Andrew Waterman
9e86b9efc9
Add provisional breakpoint support
2016-06-08 22:34:19 -07:00
Howard Mao
40ab0a7960
fix TL width adapter and make it easier to switch inner data width
2016-06-08 15:38:39 -07:00
Donggyu Kim
99b257316e
replace emulator with verilator for chisel3
2016-06-08 02:43:54 -07:00
Howard Mao
2cd897e240
Revert "include the unmatched field in CDEMatchError"
...
This reverts commit ff2937a788
2016-06-07 16:13:01 -07:00
Howard Mao
8db27a36c4
fix Tile reset power on behavior
2016-06-07 11:06:38 -07:00
Wesley W. Terpstra
5495705acf
Configs: enable AHB for FPGAs
2016-06-06 21:36:09 -07:00
Wesley W. Terpstra
ef27cc3a33
RocketChip: handle atomics only if needed
2016-06-06 21:36:03 -07:00
Wesley W. Terpstra
3e0ec855cf
RocketChip: add ahb mem interface
2016-06-06 21:35:59 -07:00
Wesley W. Terpstra
d2b505f2d2
RocketChip: rename mem to mem_axi in preparation for new bus type
2016-06-06 21:35:55 -07:00
Wesley W. Terpstra
2086c0d603
Configs: add a parameter to control the memory subsystem interface
2016-06-06 21:35:43 -07:00
Wesley W. Terpstra
2ddada1732
ahb: add mmio_ahb option
2016-06-06 21:35:39 -07:00
Wesley W. Terpstra
31f1dcaf84
ahb: rename mmio outputs to mmio_axi
2016-06-06 21:35:34 -07:00
Wesley W. Terpstra
7a24527448
ahb: make MMIO channels specifiy bus type (we will have more than one bridge)
2016-06-06 21:35:30 -07:00
Wesley W. Terpstra
f3a557b67b
ahb: AHB parameters should be site specific
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Conflicts:
src/main/scala/Configs.scala
2016-06-06 21:35:24 -07:00
Howard Mao
ff2937a788
include the unmatched field in CDEMatchError
2016-06-06 11:23:20 -07:00
Andrew Waterman
d24c87f8ba
Update PLIC/PRCI address map ( #124 )
2016-06-06 04:51:55 -07:00
Andrew Waterman
ece3ab9c3d
Refactor AddrMap and its usage ( #122 )
2016-06-03 17:29:05 -07:00
Andrew Waterman
c8338ad809
Instantiate Debug Module ( #119 )
2016-06-02 10:53:41 -07:00
Andrew Waterman
44a216038f
Use more generic TileLinkWidthAdapter
2016-05-27 13:38:13 -07:00
Andrew Waterman
10f0e13c25
Use more parsimonious queue depths
2016-05-26 18:04:22 -07:00
Andrew Waterman
3cc236e9c4
By default, use same TileLink width everywhere
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When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
2016-05-26 18:04:01 -07:00
Wesley W. Terpstra
976d4d3184
ahb: AHB parameters should match TileLink parameters by default
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Closes #116
2016-05-25 18:01:25 -07:00
Andrew Waterman
ec0d178010
Support M-mode-only implementations
2016-05-25 15:40:53 -07:00
Andrew Waterman
e82c080c3c
Add blocking D$
2016-05-25 11:09:50 -07:00
Howard Mao
f52fc655a5
remove zscale
2016-05-19 09:43:15 -07:00
Colin Schmidt
abb0e2921b
return non-zero exit codes when an assertion fires
...
This ensures that assertion failures, which currently print a message to
the console but return a successful exit code, now will cause non-zero
exit code. This is meant to help automated tools like travis and
buildbot do a better job at catching assertions.
This impacts the various run-* targets in the simulation
directories.
2016-05-18 12:57:58 -07:00
Andrew Waterman
684d902059
Fix PLIC instantiation when S-mode is disabled
2016-05-13 11:22:46 -07:00
Andrew Waterman
6aa708bcee
Disable MMIO by default to avoid disconnected nets
2016-05-11 13:12:39 -07:00
Andrew Waterman
aac89ca1f0
Add PLIC
2016-05-10 00:27:31 -07:00
Howard Mao
df479d7935
don't make MIFTagBits a computed parameter
2016-05-08 11:04:58 -07:00
Howard Mao
3b0e9167fa
add AXI to AHB converter and more conformant HASTI RAM
2016-05-06 11:32:03 -07:00
Howard Mao
dfcb73b6c9
groundtest only needs to write to a single tohost
2016-05-03 20:21:13 -07:00
Howard Mao
4045a07eda
Remove need for separate riscv-tests for groundtest
2016-05-03 18:29:46 -07:00
Howard Mao
8f891437b5
fix CacheFillTest
2016-05-03 14:57:05 -07:00
Andrew Waterman
15f4af19cf
Remove HTIF CPU port
2016-05-03 13:55:59 -07:00
Howard Mao
487d0b356e
fixes to get groundtest working with priv-1.9 changes
2016-05-03 13:09:44 -07:00
Andrew Waterman
c7c8ae5468
Instantiate PRCI block
2016-05-02 18:08:33 -07:00
Andrew Waterman
6d1e82bddf
Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port
2016-05-02 15:21:55 -07:00
Andrew Waterman
c4d2d29e80
Stub out debug module, rather than leaving it floating
2016-04-30 22:37:39 -07:00
Andrew Waterman
46bbbba5e6
New address map
2016-04-30 20:59:36 -07:00
Andrew Waterman
d0aa4c722d
More WIP on new memory map
2016-04-28 16:15:31 -07:00
Andrew Waterman
1f211b37df
WIP on new memory map
2016-04-27 14:57:54 -07:00
Colin Schmidt
48170fd9aa
add default cases to configs that use CDEMatchError
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this avoids filling in the stack trace every time
a config doesn't contain the parameter
2016-04-22 12:14:58 -07:00
Howard Mao
f7af908969
put memory into the address map and no longer use MMIOBase
2016-04-21 18:53:16 -07:00
Howard Mao
c5838dd9b3
Fix narrow read/write behavior for AXI converters and fix L2 bugs
...
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.
There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.
There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
2016-04-12 15:39:15 -07:00
Andrew Waterman
b43a85e2e8
Make ExampleSmallConfig/DefaultRV32Config smaller
2016-04-01 18:18:08 -07:00
Andrew Waterman
6878e3265f
Default RowBits to TileLink width, not XLen
2016-04-01 18:18:08 -07:00
