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Author SHA1 Message Date
Wesley W. TerpstraandGitHub 7f96da2288 ECC: support poison during encode (#1166) 
This makes it possible to update an ECC-protected word while
retaining the fact that the value has an ECC error.
 2018-03-21 16:29:24 -07:00
Wesley W. TerpstraandGitHub 95294bbdcb PatternPusher: put data at correct address when misaligned (#1249) 2018-02-23 15:20:56 -08:00
Wesley W. TerpstraandHenry Cook ef3addee7b diplomacy: put full module + instance path into graphml Description 2018-02-21 14:43:47 -08:00
Wesley W. TerpstraandGitHub bb1976552f Merge pull request #1238 from freechipsproject/error-bifurcate 
Error: don't be an exception wrt. caching
 2018-02-15 22:19:27 -08:00
Wesley W. Terpstra dcfbdabe60 CacheCork: better document edge conditions 2018-02-15 19:14:30 -08:00
Wesley W. Terpstra ecd069dca4 tilelink: allow FIFO caches 
Probably not a smart thing to build, but not illegal!
 2018-02-15 19:09:37 -08:00
Wesley W. Terpstra acecc407a5 HellaCache: we do NOT really support probe below the block size! 
If we did, you would somehow have to retain ownership of the
unprobed parts of the block, in case they happened to be dirty.
 2018-02-15 19:08:43 -08:00
Wesley W. Terpstra fa412246b3 Error: don't be an exception wrt. caching 
Prior to this PR, the error device was allowed to be cached by
multiple actors despite never probing any of them. This is a
pretty unusual set of properties that has caused us trouble
several times now in the past.

Let's instead put the Error device into one of two very well
established categories: a straight-up MMIO device or a tracked
memory region.
 2018-02-14 23:02:55 -08:00
Wesley W. TerpstraandGitHub c32150b994 ResetCatchAndSync: work also in the context of a RawModule (#1202) 2018-01-19 19:45:52 -08:00
Wesley W. TerpstraandGitHub f6f5606f8e diplomacy: run user instantiate() method after nodes are initialized (#1198) 2018-01-18 14:57:47 -08:00
Wesley W. TerpstraandGitHub 5854fb5f7c SourceShrinker improvements (#1197) 
* SourceShrinker: preserve FIFO guarantees of slaves

* tilelink: document that Releases can use TtoT, BtoB, and NtoN

TtoT is needed for write-through caches.
 2018-01-17 18:02:19 -08:00
Wesley W. Terpstra f749e986cf coreplex: fix TL MMIO port example 2018-01-05 12:29:47 +01:00
Wesley W. TerpstraandGitHub a542ae687e ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144) 2017-12-08 17:35:14 -08:00
Wesley W. TerpstraandGitHub c2a0319dc4 Merge pull request #1151 from freechipsproject/error-atoms 
Error atomics
 2017-12-08 17:34:55 -08:00
Wesley W. Terpstra efc793d52e CloneModule: must be public to be used in pattern matches 2017-12-08 14:57:08 -08:00
Wesley W. Terpstra 2ca03384ec diplomacy: skip anonymous class names 2017-12-08 14:36:12 -08:00
Wesley W. Terpstra 18b8a61775 Error device: require explicit control of atomic and transfer sizes 2017-12-08 13:41:09 -08:00
Wesley W. Terpstra 6a0150aad7 Error device: mark executable to support testing erroneous I$ refill 2017-12-08 12:38:06 -08:00
Wesley W. TerpstraandGitHub b8098d18be diplomacy: remove the :=? operator in favour of magic :*=* (#1139) 
The reason for the :=? operator was for when you have an adapter chain
whose direction of cardinality you could not know. We used explicit
directives to tell these compositions which way to go.

Unfortunately, that makes the API leaky. You think the chain of adapters
is just one adapter, but you have to use strange Cardinality scopes to
use it. That's just bad.

The new :*=* just automagically figures it out from the graph.
 2017-12-01 18:28:37 -08:00
Wesley W. TerpstraandGitHub dedf396915 groundtest: connect the ibus to a fictitious master (#1140) 2017-12-01 18:28:24 -08:00
Wesley W. TerpstraandGitHub 4bac8be483 Merge pull request #1094 from freechipsproject/in-situ-unit-tests 
In situ unit tests
 2017-12-01 13:27:30 -08:00
Wesley W. Terpstra 8781d2b2e7 diplomacy: provide a val name for all LazyModule constructions 2017-12-01 11:28:21 -08:00
Wesley W. Terpstra a3e44375c6 ValName: 'lazy val' now also counts for providing a name 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra fe8d557751 PeripheryBus: automatically disappear when not used 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra 93c8010aca FrontBus: automatically disappear when not used 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra e489c4226e diplomacy: remove node arity and allow empty Nexus nodes (Xbars) 
This removes the mostly obsolete 'numIn/Out' range restrictions on nodes.
It also makes it possible to connect optional crossbars that disappear.

val x = TLXbar()
x := master
slave := x

val y = TLXbar()
x :=* y // only connect y if it gets used

This will create crossbar x, but crossbar y will disappear.
 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra 6a25a3b7ac tilelink: we can have helper objects for terminal nodes now too! 
The new rule is you should have an object.apply method if you only have a
single .node.
 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra 2092cb4ec8 diplomacy: reprotect Node bundles after module construction is completed 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra fdeed7bbb3 unittest: add an API for describing LazyModule unit tests 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra cc789e9063 diplomacy: protect more of the unstable API 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra 8ed9e78903 diplomacy: support cloning of LazyModules 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra b43bcdfcd1 CloneModule: beat chisel into submission 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra 1f23f9f865 diplomacy: categorize parameter resolution by direction+side 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra fbbfc9c096 diplomacy: include edge type in inward/outward node handles 
This is necessary capture the node implementation in the handle,
which is in turn necessary to support cloning a Node.
 2017-12-01 11:26:58 -08:00
Wesley W. TerpstraandGitHub ea03f71f97 Merge pull request #1135 from freechipsproject/decoupled-loop-fix 
TileLink compliance: d_bits may not depend on d_ready
 2017-11-30 18:21:37 -08:00
Wesley W. Terpstra 35506279af regmapper: fix d_ready => d_bits loop in RegField.bytes 
RegField.bytes updates only those bytes which are written every cycle.
However, there was a bug that it would try to return the updated value on reads.
This led to another TL-spec violating combinational path, just like the Debug module.
 2017-11-30 16:38:45 -08:00
Wesley W. Terpstra fc1f5be316 Debug: fix a latent combinational loop (d_ready => d_bits) 
When passed a Wire, WNotify outputs that wire on reads wire => d_bits.
Furthermore, it updates the Wire when a write occures d_ready => wire.

These registers should be returning undefined value on read, anyway.
 2017-11-30 16:36:45 -08:00
Wesley W. TerpstraandGitHub a8d573beeb Merge pull request #1123 from freechipsproject/dts-global 
DTS global
 2017-11-20 19:09:03 -08:00
Wesley W. Terpstra 6f3ff634f2 DTS: collect common DTS nodes and move timebase-frequency to cores 
Putting the common DTS nodes into a shared object makes them get
emitted only one time. Plus it's better style.

timebase-frequency should really have been in the cpu nodes in the
first place according to the spec anyway. I was foolishly trying to
save bytes. However, now we really want it there in case it differs.
 2017-11-20 18:09:57 -08:00
Wesley W. Terpstra 3b299397db diplomacy: bind resources to outer-most binding 
This is probably the wrong thing to do, but it is expedient for now.
We need a better way to do cross-coreplex visibility.
 2017-11-20 17:42:08 -08:00
Wesley W. Terpstra 44f99cd9a5 diplomacy: eliminate redundant bindings 2017-11-20 17:42:08 -08:00
Wesley W. Terpstra baa31edf7d RocketTile: if the dcache is incoherent, report it in DTS 2017-11-20 17:42:06 -08:00
Wesley W. TerpstraandGitHub 342dd82fcf Merge pull request #1119 from freechipsproject/verify-blocker-width 
Verify blocker width
 2017-11-18 15:45:24 -08:00
Wesley W. Terpstra ec809483b0 BusBypass: assert fail if the widths of the two slaves do not match 2017-11-18 14:37:27 -08:00
Wesley W. Terpstra c475c78c2f BusBlocker: don't provide an (incorrect) default value for width 2017-11-18 14:33:00 -08:00
Wesley W. Terpstra 7a1937242a coreplex: provide correct bus-width for ITIM blockers 2017-11-18 14:32:37 -08:00
Wesley W. TerpstraandGitHub 61ef560c75 tilelink: don't pollute TLParamters with AtomicAutomata's implementation (#1111) 2017-11-14 17:49:10 -08:00
Wesley W. TerpstraandGitHub 8b79f0394e Merge pull request #1105 from freechipsproject/axi4-xbar 
axi4: add an Xbar
 2017-11-14 16:18:23 -08:00
Wesley W. TerpstraandGitHub 509a48c9c9 TLToAXI4: block TL early source re-use before it goes to AXI4 (#1110) 
This is a follow-up to PR #1108.

Rather than increasing the number of transactions we allow to be inflight,
instead just block TL when early source re-use happens. This is a better
fix since it means we don't pay mostly wasted downstream hardware to handle
an additional transaction inflight that almost never happens.
 2017-11-14 16:08:43 -08:00
Wesley W. Terpstra e370934c50 AXI4Xbar: reduce number of special cases 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 9004ecdf25 unittest: include AXI4Xbar in regression 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 5875017956 axi4: add an Xbar 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 72c89f7e30 axi4: add a Filter suitable for manipulating test visibility 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra bfc0ba679a axi4: add a Delayer for unit tests 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 1902ba063a Filter: can claim to be out-of-order when you are not 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 58a93e2100 AXI4SRAM: handy helper object 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 353ddffc11 RAMModel: add a convenience object 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra 7cfb69e2d5 Queue: silence some warnings 2017-11-14 15:09:09 -08:00
Wesley W. TerpstraandGitHub 147fad6387 Fix AXI4 FIFO ordering for masters with early source reuse (#1108) 
* TLToAXI4: fix WaR for single-source FIFO masters
* TLToAXI4: fix potential counter overflow => WaR hazard

If you have a FIFO master with 2^n-1 sources that performs early
source re-use, the old code could potentially break FIFO order.
 2017-11-13 20:32:09 -08:00
Wesley W. TerpstraandGitHub 0cfa801bfc coreplex: allow MMIO to be misaligned (#1103) 2017-11-10 15:12:28 -08:00
Wesley W. TerpstraandGitHub a061b16ee3 coreplex: fix typo (#1104) 2017-11-10 15:11:56 -08:00
Wesley W. TerpstraandGitHub 50ce3f5086 Merge pull request #1097 from freechipsproject/itim-error 
More ITIM error-handling improvements
 2017-11-09 00:17:48 -08:00
Wesley W. TerpstraandGitHub b59880fe8e Fragmenter: add an option for earlyAck only on PutFulls (#1095) 
Fragmenter: add a third case for earlyAck (PutFulls only)

It seems quite common to have a device that is backed by ECC. When
performing a multibeat PutPartial, these devices can exhibit their
first error on the last beat (if it had an incomplete write mask
for that beat, which required read-write-modifying corrupted data).

Generally, these devices have ECC granularity <= the bus width. In
those cases, if you send a PutFull, the first beat carries the
error value for the whole burst. Consider:
  If the PutFull was below the granularity, it was a single beat.
  If the PutFull was multi-beat, it exceeds the granularity.

Therefore, an important variation on the earlyAck optimization is
the case where only PutFulls receive an earlyAck.
 2017-11-08 15:31:19 -08:00
Wesley W. TerpstraandGitHub 1f5fb5d643 Merge pull request #1091 from freechipsproject/atomic-automata-errors 
tilelink: AtomicAutomata should OR the Get error with the Put error
 2017-11-06 13:58:02 -08:00
Wesley W. Terpstra 7cc7cd5992 tilelink: AtomicAutomata; add errors to the unit test 2017-11-06 12:05:44 -08:00
Wesley W. Terpstra 88234ead0d tilelink: generalize ErrorEvaluator to more than just address patterns 2017-11-06 11:53:09 -08:00
Wesley W. Terpstra 25ea7fa852 tilelink: AtomicAutomata should OR the Get error with the Put error 2017-11-06 11:31:23 -08:00
Wesley W. TerpstraandGitHub dcf67b49fa BusBypass: only stall A once the last beat is accepted (#1090) 
When switching ports, the bypass stalls new messages until all
outstanding messages have received their responses. However, this
stall must NOT stop the remaining beats of a partially sent request.
 2017-11-06 11:13:15 -08:00
Wesley W. TerpstraandGitHub 16116991e7 Fix stateless caching (#1084) 
* tilelink: ToAXI4 should format it's error message

* WithStatelessBridge: mark the memory bus incoherent and cacheable

... and hope that the user doesn't put more than one master down.
 2017-11-01 11:05:56 -07:00
Wesley W. TerpstraandGitHub 4ccdbecb63 Async covers (#1085) 
* cover: support covering cross-product of ready-valid

* tilelink: AsyncCrossing now has covers for all flow control logic
 2017-11-01 11:03:45 -07:00
Wesley W. TerpstraandGitHub 84145959e1 tilelink: fix error fragmentation from multibeat to multibeat (#1082) 
Unfortunately, dLast is not actually correct for AccessAckData.
dFragnum is 0 for all the subbeats in the multibeat=>multibeat case.
 2017-10-31 17:34:46 -07:00
Wesley W. TerpstraandGitHub 8ec06151b0 interrupts: Crossing should use asynchronously reset registers (#1080) 
Otherwise you can get interrupts wedged high from a domain that has
not yet been clocked/powered up.
 2017-10-31 16:29:06 -07:00
Wesley W. TerpstraandGitHub eaac0f6598 Merge pull request #1078 from freechipsproject/error-support 
Error support
 2017-10-30 22:21:20 -07:00
Wesley W. Terpstra 45a904b396 ahb: ignore hrdata on an AHB error 
From the AHB spec:
 "A slave only has to provide valid data when a transfer completes with an OKAY
  response. ERROR responses do not require valid read data."
 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra 6318d7d44c ahb: inject fuzzy errors 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra 2912a76a2b axi4: inject fuzzy errors 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra e8ed450f13 unit tests: do not use LFSR16 which has a common seed! 
We want each LFSR to generate independent noise.
 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra ec70e5fb02 apb: inject fuzzy errors 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra 0280a1f218 tilelink: add the ErrorEvaluator, a test bench error helper 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra 2d12ddb4ed tilelink: ToAXI4 makes R channel errors sticky 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra d6f1612812 tilelink: ToAHB should make read errors sticky as well 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra 4c9d9c6331 tilelink: optimize WidthWidget error circuit to nothing 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra 0992a459be tilelink: Fragmenter should combine errors 2017-10-30 21:09:42 -07:00
Wesley W. Terpstra 13d0bf6808 tilelink: Monitor now enforces spec-defined error rules 2017-10-30 11:27:07 -07:00
Wesley W. TerpstraandGitHub 5ca04a5c41 Merge pull request #1077 from freechipsproject/node-style 
diplomacy: switch adapter methods to node style
 2017-10-28 13:15:28 -07:00
Wesley W. Terpstra a954f020a9 diplomacy: use new node style chaining 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra 6aac658184 diplomacy: convert all helper objects to return nodes 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra 41705808dd Bus: remove deprecated crossing attach methods 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra 7cf5d4aa90 diplomacy: define only primary node types 2017-10-28 11:16:56 -07:00
Wesley W. Terpstra eeb11a2693 coreplex: eliminate dead code 2017-10-27 01:13:35 -07:00
Wesley W. TerpstraandGitHub 9f83db998e tile: don't chain too many unneeded TileLink adapters (#1075) 2017-10-27 01:12:58 -07:00
Wesley W. TerpstraandGitHub e12bdfdf9b coreplex: attach example external interrupts (#1076) 
Fixes #1071
 2017-10-27 01:12:42 -07:00
Wesley W. TerpstraandGitHub 13981379c4 CoreplexClockCrossing: add a helper method to decide if a clock is useul (#1074) 2017-10-26 23:39:56 -07:00
Wesley W. TerpstraandGitHub 91d8a97f1a Merge pull request #1065 from freechipsproject/better-bus-wrappers 
Better crossings deployed to bus and tile wrappers
 2017-10-26 16:48:38 -07:00
Wesley W. Terpstra 1d8e539362 coreplex: confirm crossings actually cross the right boundary 2017-10-26 15:53:01 -07:00
Wesley W. Terpstra 60284082e7 diplomacy: add a hook for injecting code into LazyModule.module scope 2017-10-26 15:19:05 -07:00
Wesley W. Terpstra a060c37173 diplomacy: expose the API to query a Node for its neighbours 2017-10-26 15:08:06 -07:00
Wesley W. Terpstra e2d6d4d725 diplomacy: eliminate bindings dead-code 2017-10-26 15:02:21 -07:00
Wesley W. Terpstra 9e33ccdb05 rocket: clarify intent of boundaryBuffers and move to RocketTile 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra e76e0f6dce interrupts: add debugstring to nodes to show sync depth in graphml 2017-10-26 13:58:52 -07:00