Fix stateless caching (#1084)

* tilelink: ToAXI4 should format it's error message

* WithStatelessBridge: mark the memory bus incoherent and cacheable

... and hope that the user doesn't put more than one master down.

src/main/scala/coreplex/Configs.scala

@@ -155,7 +155,9 @@ class WithStatelessBridge extends Config((site, here, up) => {
   case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { coreplex =>
     implicit val p = coreplex.p
     val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes))
-    (ww.node, ww.node, () => None)
+    val cc = LazyModule(new TLCacheCork(unsafe = true))
+    cc.node :*= ww.node
+    (ww.node, cc.node, () => None)
   })
 })
 

src/main/scala/tilelink/ToAXI4.scala

@@ -14,7 +14,7 @@ case class TLToAXI4Node(stripBits: Int = 0)(implicit valName: ValName) extends M
     p.clients.foreach { c =>
       require (c.sourceId.start % (1 << stripBits) == 0 &&
                c.sourceId.end   % (1 << stripBits) == 0,
-               "Cannot strip bits of aligned client ${c.name}: ${c.sourceId}")
+               s"Cannot strip bits of aligned client ${c.name}: ${c.sourceId}")
     }
     val clients = p.clients.sortWith(TLToAXI4.sortByType _)
     val idSize = clients.map { c => if (c.requestFifo) 1 else (c.sourceId.size >> stripBits) }