riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex: attach example external interrupts (#1076) 

Fixes #1071
This commit is contained in:
Wesley W. Terpstra 2017-10-27 01:12:42 -07:00 committed by GitHub
parent 13981379c4
commit e12bdfdf9b
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/coreplex/InterruptBus.scala
View File

@ -81,5 +81,5 @@ trait HasExtInterruptsModuleImp extends LazyModuleImp with HasExtInterruptsBundl
val outer: HasExtInterrupts
val interrupts = IO(UInt(INPUT, width = outer.nExtInterrupts))
outer.extInterrupts.in.map(_._1).flatten.zipWithIndex.foreach { case(o, i) => o := interrupts(i) }
outer.extInterrupts.out.map(_._1).flatten.zipWithIndex.foreach { case(o, i) => o := interrupts(i) }
}