riscv/rocket-chip
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Author SHA1 Message Date
Henry Cook 63bd0b9d2a Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed. 2014-08-08 12:27:47 -07:00
Henry Cook f411fdcce3 Full conversion to params. Compiles but does not elaborate. 2014-08-08 12:21:57 -07:00
Scott Beamer d3a8a224fe README updated for new fpga flow 2014-08-07 14:52:56 -07:00
Scott Beamer e390eba8ce convert README to markdown 2014-08-07 14:50:31 -07:00
Scott Beamer 4109d7cc87 newest version of chisel needed for brams 2014-08-07 13:49:31 -07:00
Palmer Dabbelt 0fc3acb978 Update the directions on how to update Chisel 
It seems that the update process in the README is really out of date
(it refers to scala-2.8 and chisel-1.1).  I've updated it to what I
believe to be correct, which now just consists of pulling the Chisel
submodule.

Note that I tried this myself, but when I did it I also ran an "sbt
package" in the Chisel submodule top-level directory (there's no "sbt"
directory in there any more).  I believe it's not necessary to run
"sbt package", but I really know nothing about SBT...
 2014-08-05 11:56:03 -07:00
Palmer Dabbelt 693489da87 Add a note to the README about "make emulator-debug" 
I made a clean checkout of reference-chip yesterday and wasn't able to
build the debug emulator without first having built the non-debug
emulator.  I just added a note to the README to say this.
 2014-08-05 11:53:55 -07:00
Adam Izraelevitz 08d81d0892 First cut at using new chisel parameters for toplevel parameters and fpu 2014-08-01 18:09:37 -07:00
Adam Izraelevitz fcd68364ff Merge branch 'master' of github.com:ucb-bar/reference-chip into dse 
Conflicts:
	src/main/scala/ReferenceChip.scala
 2014-08-01 18:07:22 -07:00
Andrew Waterman 7bffc6c586 rename Unsigned.size to Unsigned.clog2 2014-06-14 13:58:07 -07:00
Andrew Waterman 3828c628c3 Remove vestigial control signals 2014-06-14 13:58:07 -07:00
Andrew Waterman 04593d433e clean up Int <-> Boolean conversion stuff 2014-06-14 13:58:07 -07:00
Andrew Waterman ac88ded35a Use ROMs to reduce node count and improve QoR a bit 2014-06-14 13:58:07 -07:00
Andrew Waterman 88899eafe0 Reduce node count a bit 2014-06-14 13:58:07 -07:00
Jim Lawson 0c93567dea Replace needWidth() with getWidth. 2014-06-13 14:58:52 -07:00
Jim Lawson 0020ded367 Replace needWidth() with getWidth. 2014-06-13 14:53:48 -07:00
Jim Lawson de32595fba Quick change to work with new Width class. 2014-06-13 12:00:50 -07:00
Jim Lawson a04ef4f5f4 Quick change to work with new Width class. 
Replace .width with .needWidth()
 2014-06-13 11:44:43 -07:00
Andrew Waterman 1ae7a9376c Fix unhandled LLC writeback hazard 2014-06-13 03:25:52 -07:00
Henry Cook 434da22283 Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel) 2014-05-28 17:16:49 -07:00
Henry Cook dab675b231 refactor Metadata, clean and expand coherence API 2014-05-28 16:05:48 -07:00
Henry Cook b0ccb88982 make outer cache type choice a top-level const 2014-05-28 14:46:07 -07:00
Henry Cook 3c329df7e7 refactor Metadata, clean and expand coherence API 2014-05-28 13:35:08 -07:00
Andrew Waterman 8bc1c33540 Fix BTB error (requires Chisel update) 2014-05-19 18:56:30 -07:00
Andrew Waterman 364a6de214 Use Mem instead of Vec[Reg] 2014-05-18 19:26:35 -07:00
Andrew Waterman cbb37ccc3e Use Mem instead of Vec[Reg] 2014-05-18 19:25:43 -07:00
Andrew Waterman e91e12ed88 Fix RoCC accumulator example 2014-05-14 16:17:39 -07:00
Andrew Waterman 4ca152b012 Use BundleWithConf to avoid clone method boilerplate 2014-05-09 19:37:16 -07:00
Andrew Waterman 94c1f01ec6 Deanonymize CSRFile's IO bundle 2014-05-09 19:30:57 -07:00
Andrew Waterman fd5f419eb1 use getWidth instead of width 2014-05-09 19:30:57 -07:00
Andrew Waterman 0c13c00d08 Reduce node count by avoiding elsewhen :-( 2014-05-09 19:30:57 -07:00
Andrew Waterman 8dcc0cbb53 Fix bug with multiple DecodeLogics per module 2014-05-09 19:30:57 -07:00
Henry Cook 0e39346a12 L2-specific metadataarray wrapper, hookups to tshrfile 2014-05-07 01:51:46 -07:00
Henry Cook 5bc6981414 fix metadata default, add bug TODO 2014-05-06 18:36:22 -07:00
Stephen Twigg d2a3b1dc20 Merge branch 'shapeanalysis' 2014-05-06 16:49:54 -07:00
Henry Cook f8b3117ac0 bump rocket, uncore 2014-05-06 13:10:12 -07:00
Henry Cook 7d6a642c0c correct use of function value to initialize MetaDataArray 2014-05-06 13:00:00 -07:00
Henry Cook bc3ef1011e correct use of function value to initialize MetaDataArray 2014-05-06 12:59:45 -07:00
Henry Cook 445d4f2eee bump rocket, uncore 2014-05-01 01:46:55 -07:00
Henry Cook 7f690dd9c8 parameterize metadataarray 2014-05-01 01:45:45 -07:00
Henry Cook 45172f1f37 parameterize metadataarray 2014-05-01 01:44:59 -07:00
Henry Cook ce056b4b89 client/master -> inner/outer 2014-04-29 16:50:30 -07:00
Henry Cook 0237229921 client/master -> inner/outer 2014-04-29 16:49:18 -07:00
Henry Cook 224e286dd3 New uncore config objects. Backends get their own file. Simplify fpga uncore. 2014-04-26 19:46:11 -07:00
Henry Cook 52c6de5641 DRAMSideLLCLike trait. TSHRFile. New L2 config objects. 2014-04-26 19:11:36 -07:00
Henry Cook 519b2ea2b6 New metadata result trait 2014-04-26 19:08:56 -07:00
Henry Cook 3d4273954a TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:19:25 -07:00
Henry Cook 1b156c6db9 TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:18:21 -07:00
Henry Cook 1163131d1e TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:17:05 -07:00
Henry Cook 3f53d532c2 uniquify tilelink conf val name for easier subtyping 2014-04-26 14:58:38 -07:00