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Commit Graph

3777 Commits

Author SHA1 Message Date
1583560757 fix replay bug, don't respond when cmd is a NOP 2013-10-28 22:35:18 -07:00
437f7ed4af Push hardfloat (ignore target files) 2013-09-26 20:51:19 -07:00
fc9c676fc1 add chisel and hardfloat back as sub-projects, bump other sub-projects 2013-09-26 12:01:46 -07:00
42693d43ad simplify build.sbt 2013-09-26 09:51:14 -07:00
f6d7e22c46 Push rocket (fix issue with uppermost bit of D$ req tag getting lost) 2013-09-25 11:52:01 -07:00
36b85b8ee2 Fix issue where the MSB of D$ req tag was getting lost for all agents when an accelerator was attached. 2013-09-25 11:51:10 -07:00
36dfff5ee8 Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy. 2013-09-25 01:21:41 -07:00
891e459625 Export stats pcr register (#28 currently) to the top-level 2013-09-25 01:16:32 -07:00
eb7e6f03b3 push rocket (AccumulatorExample fixes and documentation) 2013-09-24 16:33:32 -07:00
730a6ec76b AccumulatorExample now properly sets its busy bit. Also, pepper some helpful comments into AccumulatorExample 2013-09-24 16:32:49 -07:00
472b947fbe push rocket (add option to RocketConfiguration, vm, to turn off virtualk memory) 2013-09-24 16:16:12 -07:00
eb03f61058 Properly ignore target files. Push uncore (properly ignore target files) 2013-09-24 16:03:28 -07:00
20246b373e Properly ignore target files 2013-09-24 16:02:00 -07:00
81c752de84 Support disabling virtual memory 2013-09-24 13:58:47 -07:00
adc386f889 Turn off virtual memory inside RoCC base class 2013-09-24 13:58:47 -07:00
081fcc4e63 push rocket (accelerator interface fixes) 2013-09-24 10:55:22 -07:00
3532ae0b79 From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator). 2013-09-24 10:54:09 -07:00
fba0ae0fec Push rocket 2013-09-23 00:26:27 -07:00
db1e09f0d0 Fix issues with RoCC AccumulatorExample stalls on memory interface 2013-09-23 00:21:43 -07:00
324a6321bd Push tools (improve consistency: these tools will compile/test the new ISA encoding) 2013-09-22 03:24:11 -07:00
2676ea8279 Push rocket (fix some issues with RoCC although some remain) 2013-09-22 03:19:43 -07:00
158cee08af Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads) 2013-09-22 03:18:06 -07:00
b7d7ced41b Update to new ISA 2013-09-21 06:40:23 -07:00
1d2f4f8437 New ISA encoding, AUIPC semantics 2013-09-21 06:32:40 -07:00
09247c0e0b fix to sram init pins 2013-09-19 20:12:10 -07:00
c9813603ee Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2 2013-09-19 20:11:11 -07:00
cc3dc1bd0f bug fix 2013-09-19 20:10:56 -07:00
9bf10ae5d2 remove extraneous toBits (need new Chisel) 2013-09-19 15:26:36 -07:00
42970c9a99 Update Rocket 2013-09-15 04:39:52 -07:00
25ab402932 swap JAL, JALR encodings 2013-09-15 04:29:06 -07:00
628745226c Use spike disassembler riscv-dis if it exists 2013-09-15 04:25:53 -07:00
80003b3019 Support RoCC 2013-09-15 04:25:26 -07:00
110e53cb48 Revert "Add early out to multiplier"
This broke recently and I don't have time to figure out why.
2013-09-15 04:15:32 -07:00
88d1c47665 don't disassemble within chisel 2013-09-15 04:14:45 -07:00
f12bbc1e43 working RoCC AccumulatorExample 2013-09-14 22:34:53 -07:00
18968dfbc7 Move store data generation into cache 2013-09-14 16:15:07 -07:00
a0cb711451 Start adding RoCC 2013-09-14 15:31:50 -07:00
d053bdc89f Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
2013-09-12 22:34:38 -07:00
1edb1e2a0a Ignore LSB of PC 2013-09-12 17:55:58 -07:00
fbdbb01232 update to new isa; disable vector tests 2013-09-12 17:04:03 -07:00
cc7783404d Add memory command M_XA_XOR 2013-09-12 16:09:53 -07:00
59f5358435 Implement AQ/RL; move fence logic out of cache 2013-09-12 16:07:30 -07:00
243c4ae342 sync up rocket with new isa 2013-09-12 03:44:38 -07:00
95dd0d8be1 Remove DebugIO/error mode 2013-09-11 20:15:21 -07:00
b42e140e05 NetworkIOs no longer use thunks 2013-09-10 16:23:52 -07:00
1cac26fd76 NetworkIOs no longer use thunks 2013-09-10 16:15:41 -07:00
f9b85d8158 NetworkIOs no longer use thunks 2013-09-10 16:15:19 -07:00
ee98cd8378 new enum syntax 2013-09-10 10:54:51 -07:00
d06e24ac24 new enum syntax 2013-09-10 10:51:35 -07:00
6cde69e95d Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc. 2013-09-09 14:31:18 -07:00