Henry Cook
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5e2f98747f
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Merge branch 'dse'
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2014-09-06 06:10:15 -07:00 |
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Scott Beamer
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600c5d50a9
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better fix with explanation of sbt issue
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2014-09-02 15:14:56 -07:00 |
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Scott Beamer
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f9922a106b
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fixes sbt error during first run
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2014-09-02 14:34:36 -07:00 |
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Henry Cook
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b42a2ab40a
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Final parameter refactor
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2014-09-01 13:28:58 -07:00 |
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Adam Izraelevitz
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2d6aafc32e
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Merge branch 'dse' of github.com:ucb-bar/rocket-staging into HEAD
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2014-09-01 11:23:50 -07:00 |
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Sagar Karandikar
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83c6c2c9e2
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rename refs to zynq-fpga to fpga-zynq
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2014-08-29 10:26:48 -07:00 |
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Henry Cook
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6a4193cf90
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minor cache param cleanup
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2014-08-19 11:38:46 -07:00 |
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Henry Cook
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2de268b3b1
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Cache utility traits. Completely compiles, asm tests hang.
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2014-08-19 11:38:20 -07:00 |
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Henry Cook
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ca5f38ff26
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a few more fixes. some param lookups fail (here() in Alter blocks)
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2014-08-19 11:38:11 -07:00 |
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Henry Cook
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0dac9a7467
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Full conversion to params. Compiles but does not elaborate.
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2014-08-19 11:38:02 -07:00 |
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Adam Izraelevitz
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4e6d69892d
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Added initial brainstorm for parameter hierarchical flattening, does not compile ;)
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2014-08-19 11:37:50 -07:00 |
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Adam Izraelevitz
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812353bace
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Ported FPU parameters to new Chisel Parameters
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2014-08-19 11:37:27 -07:00 |
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Yunsup Lee
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4ac8e59b1f
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add .gitignore
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2014-08-18 19:27:50 -07:00 |
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Yunsup Lee
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d520846638
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add README and sbt files
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2014-08-18 19:23:10 -07:00 |
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Andrew Waterman
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7bffc6c586
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rename Unsigned.size to Unsigned.clog2
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2014-06-14 13:58:07 -07:00 |
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Andrew Waterman
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3828c628c3
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Remove vestigial control signals
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2014-06-14 13:58:07 -07:00 |
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Andrew Waterman
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04593d433e
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clean up Int <-> Boolean conversion stuff
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2014-06-14 13:58:07 -07:00 |
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Andrew Waterman
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ac88ded35a
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Use ROMs to reduce node count and improve QoR a bit
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2014-06-14 13:58:07 -07:00 |
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Andrew Waterman
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88899eafe0
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Reduce node count a bit
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2014-06-14 13:58:07 -07:00 |
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Jim Lawson
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0c93567dea
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Replace needWidth() with getWidth.
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2014-06-13 14:58:52 -07:00 |
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Jim Lawson
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de32595fba
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Quick change to work with new Width class.
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2014-06-13 12:00:50 -07:00 |
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Henry Cook
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dab675b231
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refactor Metadata, clean and expand coherence API
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2014-05-28 16:05:48 -07:00 |
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Andrew Waterman
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8bc1c33540
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Fix BTB error (requires Chisel update)
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2014-05-19 18:56:30 -07:00 |
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Andrew Waterman
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cbb37ccc3e
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Use Mem instead of Vec[Reg]
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2014-05-18 19:25:43 -07:00 |
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Andrew Waterman
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e91e12ed88
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Fix RoCC accumulator example
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2014-05-14 16:17:39 -07:00 |
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Andrew Waterman
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4ca152b012
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Use BundleWithConf to avoid clone method boilerplate
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2014-05-09 19:37:16 -07:00 |
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Andrew Waterman
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94c1f01ec6
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Deanonymize CSRFile's IO bundle
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2014-05-09 19:30:57 -07:00 |
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Andrew Waterman
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fd5f419eb1
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use getWidth instead of width
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2014-05-09 19:30:57 -07:00 |
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Andrew Waterman
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0c13c00d08
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Reduce node count by avoiding elsewhen :-(
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2014-05-09 19:30:57 -07:00 |
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Andrew Waterman
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8dcc0cbb53
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Fix bug with multiple DecodeLogics per module
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2014-05-09 19:30:57 -07:00 |
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Henry Cook
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5bc6981414
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fix metadata default, add bug TODO
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2014-05-06 18:36:22 -07:00 |
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Henry Cook
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7d6a642c0c
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correct use of function value to initialize MetaDataArray
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2014-05-06 13:00:00 -07:00 |
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Henry Cook
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7f690dd9c8
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parameterize metadataarray
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2014-05-01 01:45:45 -07:00 |
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Henry Cook
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519b2ea2b6
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New metadata result trait
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2014-04-26 19:08:56 -07:00 |
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Henry Cook
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1b156c6db9
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TileLinkIO.GrantAck -> TileLinkIO.Finish
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2014-04-26 15:18:21 -07:00 |
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Henry Cook
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fc825c7103
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MetaData & friends moved to uncore/
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2014-04-23 16:23:51 -07:00 |
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Henry Cook
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f4d326b8d7
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Prep in HellaCache for extracting MetaData to uncore
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2014-04-23 15:43:31 -07:00 |
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Henry Cook
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5c62cff2ce
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put replacement policy in uncore and minor nbdcache cleanups
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2014-04-22 16:53:20 -07:00 |
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Andrew Waterman
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09e2ec1f9e
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Fix sign of remainder when dividing by zero
h/t chris
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2014-04-18 16:32:57 -07:00 |
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Henry Cook
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1fa505f9ff
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remove superfluous AVec object
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2014-04-16 17:19:32 -07:00 |
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Andrew Waterman
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3520620fbd
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Remove D$ -> BTB path
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2014-04-15 23:05:02 -07:00 |
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Andrew Waterman
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de492b3cf7
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Fix critical path through integer scoreboard
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2014-04-15 21:28:13 -07:00 |
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Henry Cook
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444d0449e3
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io.cnt bug in serializer
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2014-04-14 17:13:13 -07:00 |
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Henry Cook
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1da8ef2ddf
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Added serdes to decouple cache row size from tilelink data size
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2014-04-10 12:34:12 -07:00 |
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Henry Cook
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910b3b203a
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removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
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2014-04-10 12:32:44 -07:00 |
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Henry Cook
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ebdc0a2692
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merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
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2014-04-10 12:09:52 -07:00 |
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Stephen Twigg
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e90f2484aa
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Sync with riscv-opcodes (csr register mapping)
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2014-04-08 15:48:37 -07:00 |
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Andrew Waterman
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3ed8adf032
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Add early out for MUL[W] (not MULH[[S]U])
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2014-04-07 23:48:02 -07:00 |
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Andrew Waterman
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927287da34
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Bypass RAS push/pop
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2014-04-07 23:47:53 -07:00 |
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Andrew Waterman
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f235fa0db6
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Move branch resolution to M stage
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2014-04-07 15:58:49 -07:00 |
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