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Author SHA1 Message Date
Wesley W. TerpstraandGitHub 87a5665e43 axi4: only block writes if SAME master has outstanding reads (#782) 
* axi4: only block writes if SAME master has outstanding reads
* tilelink2: ToAXI4 rename variable
TL uses sources, not IDs like AXI. Keep it less confusing.
* tilelink2: ToAXI4 improve stall circuit delay
Don't bother decoding the AXI ID to compute stall.
 2017-06-05 16:54:00 -07:00
Wesley W. TerpstraandGitHub 4679545b60 travis: front-load the longer running tests and tolerate no output (#779) 2017-06-02 20:41:26 -07:00
Wesley W. TerpstraandGitHub 63b1f4f047 Merge pull request #777 from freechipsproject/print-axi-ids 
coreplex: Improve memory map and AXI ID map output
 2017-06-02 18:52:55 -07:00
Wesley W. Terpstra e0741a2097 axi4: don't map unused masters into TL source ID space 2017-06-02 16:30:16 -07:00
Wesley W. Terpstra 6b7a9f0c95 Revert "Bump firrtl to get performance bug fixes (#772)" 
This reverts commit 8e45dd9352.
We will bump firrtl once chisel uses the same library versions.
 2017-06-02 15:52:32 -07:00
Wesley W. Terpstra 80c63c0da6 rocket: include hartid in cache master names 2017-06-02 15:52:23 -07:00
Wesley W. Terpstra d25ad10592 diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
Wesley W. Terpstra 475ac93cdf coreplex: print memory map using DTS, also write a JSON for it 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra ae8734da05 diplomacy: report cacheability in ResourceAddress 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra 985d9750e6 tilelink2: Xbar QoR improvement 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra 9317a00896 tilelink2: ToAXI4, sort and print AXI IDs used 2017-06-02 14:27:37 -07:00
Wesley W. TerpstraandGitHub 38e6512c0f Merge pull request #775 from freechipsproject/unify-only-at-end 
Unify only at end
 2017-06-01 17:16:48 -07:00
Wesley W. Terpstra eb14329c63 tilelink2: only combine managers of the same resources 2017-06-01 15:34:43 -07:00
Wesley W. Terpstra 1f531b1593 tilelink2: improve round robin arbiter QoR 2017-06-01 15:34:40 -07:00
Wesley W. Terpstra 5994714970 diplomacy: move manager unification to meta-data only 
Now that PMA circuits already perform address unification, there is
no QoR gained by throwing away the true and complete diplomatic
address+node information. Defer the unification to pretty printing
the DTS address map only.
 2017-06-01 15:30:20 -07:00
Wesley W. Terpstra 0fe625c52f diplomacy: improve PMA circuit QoR 2017-06-01 15:30:20 -07:00
Wesley W. TerpstraandGitHub dfb6340927 Merge pull request #755 from freechipsproject/verilator-plusargs 
Verilator plusargs
 2017-06-01 14:34:09 -07:00
Wesley W. Terpstra 6a7e6ab325 plusarg_reader: support verilator 2017-06-01 10:59:45 -07:00
Wesley W. Terpstra 9eae1fa377 verilator: bump to version 3.904 2017-06-01 10:59:39 -07:00
Wesley W. TerpstraandGitHub 7f1d3c445f Plusargs -- tilelink timeout detection from the command line (#752) 
* util: PlusArg gives Chisel access to the command-line

* tilelink2: add a progress watchdog to Monitors
 2017-05-18 22:49:59 -07:00
Wesley W. TerpstraandGitHub 20704b1454 Merge pull request #753 from freechipsproject/debug_tests 
Debug Tests
 2017-05-18 22:20:21 -07:00
Wesley W. TerpstraandGitHub 55e8d28868 Merge pull request #747 from freechipsproject/try-travis-stages 
try using a new travis staging feature
 2017-05-18 14:14:54 -07:00
Wesley W. Terpstra 748a48f667 unittest: balance the run times of the tests 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra bea2489507 unittest: make overall test duration configurable 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra c8ba6b2feb unittests: accept a configurable number of transactions to run 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra f6f40b1442 unit tests: all should accept timeout override 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra 4acc302158 unittest: disable XBar test from regression (covered by other tests) 2017-05-17 14:02:59 -07:00
Wesley W. Terpstra 8c3736e0dc tilelink2: remove ready-valid fuzzer obsoleted by TLDelayer 2017-05-17 06:47:21 -07:00
Wesley W. Terpstra 1f2236cdb3 diplomacy: appease Jack by removing unused 1st bundles argument 2017-05-17 06:46:07 -07:00
Wesley W. Terpstra f2d16d49c2 tilelink2: don't widen TLMonitor interface unnecessarily 2017-05-17 06:29:03 -07:00
Wesley W. Terpstra 191dad7800 diplomacy: provide connect access to edges without bundles 
Forcing the bundles to exist early can mess up module ownership.
 2017-05-17 06:29:03 -07:00
Wesley W. TerpstraandGitHub 65053978dc Merge pull request #745 from freechipsproject/tile-xbar 
Tile xbar
 2017-05-17 06:28:37 -07:00
Wesley W. TerpstraandGitHub ad087dd18d Merge pull request #742 from ucb-bar/true-rational 
RationalCrossing: now supporting true rational N:M crossings
 2017-05-15 15:51:35 -07:00
Wesley W. Terpstra 3e2b477c0a rational: adjust comments and add a case for N:M 2017-05-14 15:16:33 -07:00
Wesley W. Terpstra 2119df5a60 vsrc: add ClockDivider3 used to simulate unaligned clocks 2017-05-14 15:05:55 -07:00
Wesley W. TerpstraandGitHub 05e7501e7a build: include chiselName and give an example of using it (#738) 2017-05-12 06:25:58 -07:00
Wesley W. TerpstraandGitHub 18725a05b0 DTS tweaks (#740) 
* rocket: do not report 's' in isa string

* rocket: report the micro-architecture of the core
 2017-05-12 05:32:57 -07:00
Wesley W. TerpstraandGitHub 9720a53eae Merge pull request #735 from ucb-bar/early-ack-frag-fix 
tilelink2: keep earlyAck Fragmenter sources distinct
 2017-05-09 18:22:59 -07:00
Wesley W. Terpstra 3eaa973da7 tilelink2: add earlyAck to regression 2017-05-09 17:35:26 -07:00
Wesley W. Terpstra 3e7bdcbf5e tilelink2: Fragmenter should ignore error when not valid 2017-05-09 17:35:26 -07:00
Wesley W. Terpstra 43c9f5fe7e tilelink2: keep earlyAck Fragmenter sources distinct 2017-05-09 17:35:22 -07:00
Wesley W. TerpstraandGitHub fd76f45f65 Merge pull request #731 from ucb-bar/axi-zero-width 
axi4: Support AXI4-Lite properly
 2017-05-08 10:48:32 -07:00
Wesley W. Terpstra 2d8a49cc06 tilelink2: Fragmenter client must request global FIFO 2017-05-08 00:56:45 -07:00
Wesley W. Terpstra 36f4584bb1 axi4: Test AXI4-Lite in regression 2017-05-08 00:31:35 -07:00
Wesley W. Terpstra 3209e58845 axi4: SRAM support 0 userBits 2017-05-08 00:31:14 -07:00
Wesley W. Terpstra db76ff2d86 axi4: Deinterleaver must gather R also for single ID 
In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra 8fc27b0bf2 axi4: IdIndexer; a single ID does NOT imply no response interleaving 
Some slaves may never send R until you process their B.
Thus, while there is no read response interleaving, there
is still interleaving between R and B, which breaks AXI4ToTL.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra 4847c32599 tilelink: ToAXI4 - must interlock till last beat 
AXI4 makes no guarantee that bursts are handled atomicly.
Thus, you could be part-way through a read burst and suddenly
a write cuts ahead and is visible later, violating FIFO.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra 8169ba6411 axi4: IdIndexer now handles 0-width IDs 2017-05-08 00:17:02 -07:00
Wesley W. Terpstra fe280187a1 axi4: Fragmenter cuts all input channel readys 
AXI4 forbids any input to lead combinationally to an output.For the AXI4ToTL
direction, front-load the cuts for {AW, AR, W}.readyAXI4ToTL makes the R and
B channels irrevocable.
 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 3d06f01a2c rocket: turn on early ack for ITIM 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 58a4529cc5 axi4: the last missing piece for safe FIFO ordering 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra b0b5601e8d axi4: ToTL correct error handling 
If there is an illegal AWADDR = 0x2 on a 32-bit bus, remapping it
to an aligned address on the error device may make the mask
inconsistent with the address + size.
 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 661015a78d axi4: switch arbiter to round robin 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 976af7a8c7 tilelink2: better width inference for {left,right}OR 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 40f18e6e43 diplomacy: optimize IdRange overlap detection 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 30f1f1e7c7 rocket: turn on early ack for DTIM 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra 6ee69454c3 tilelink2: Fragmenter now supports early Ack 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra e09fa866b7 tilelink2: FIFOFixer should NOT change client request status 
Just because some clients are not FIFO does not matter. Downstream
FIFOFixers will still present a legitimate single domain to those
client who care.
 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra a71f708dc7 rocketchip: move the Error device to 0x3000 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra d27e1928dd axi4: make maxFlight a per-master parameter 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra e1a072a644 axi4: massage test cases into shape again 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra 9f08c484bd tilelink2: ToAXI4 provide FIFO order semantics 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra 61a6f94196 axi4: get unit tests legal again 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra bf5cb396b9 rocketchip: relax mmio no-interleaving requirement 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra 24f577c156 axi4: Deinterleaver ensures R channel ID does not change till last 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra b4188ee625 axi4: ToTL supporting pipelined MMIO 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra ca2cb033cd rocketchip: fix uses of AXI4 Fragmenter 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra e100a943ea axi4: simplify Fragmenter by using user bits 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra 7a1d107c9e rocketchip: include an ErrorSlave by default 2017-05-01 22:53:37 -07:00
Wesley W. Terpstra 641a4d577a tilelink2: Error device for returning errors on demand 2017-05-01 22:53:02 -07:00
Wesley W. Terpstra a580b17ece axi4: IdIndexer => reduce number of needed ids 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra 06efc01d96 axi4: an adapter to remove user bits 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra f1217519f1 axi4: RegisterRouter; concurrent response illegal in AXI 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra 5163ccd11f axi4: RegisterRouter supports user bits 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra de6ea9b442 axi4: support user bits in SRAM 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra 396ecacda4 AXI4: add an optional user bundle field 2017-05-01 22:53:01 -07:00
Wesley W. TerpstraandGitHub f3ab23d068 dcache: fix stupidly wrong crossing comparison (#703) 2017-04-25 09:18:41 -07:00
Wesley W. TerpstraandGitHub 4807ce7ced dcache: put a flow Q to absorb back-pressure without restarting pipeline (#701) 
* dcache: put a flow Q to absorb back-pressure without restarting pipeline

When used with a RationalCrossing, pipelined MMIO does not come out cleanly.
The first beat works, but if the second beat gets stalled, the pipeline is
restarted. This is a quick hacky test to absorb the beats. Perhaps a better
fix can be made to achieve the same effect.

* dcache: provision as few stages as possible
 2017-04-24 23:28:04 -07:00
Wesley W. TerpstraandGitHub 9c1d126965 Allow speculative fetch to uncacheable memory if it hits in I$ (#700) 
@aswaterman it's in
 2017-04-24 19:12:37 -07:00
Wesley W. TerpstraandGitHub 11ff4dfbb9 rocket: seip (int 9) is only present if VM is enabled (#699) 2017-04-24 15:58:33 -07:00
Wesley W. TerpstraandGitHub d0f3004097 tilelink2: help tools save some registers in the WidthWidget (#691) 2017-04-24 15:13:58 -07:00
Wesley W. TerpstraandGitHub b4d17c76d1 coreplex: make rational+synchronous crossing configurable (#688) 2017-04-19 16:16:05 -07:00
Wesley W. TerpstraandGitHub db5d0737f0 Merge pull request #682 from ucb-bar/jchang 
Add hooks to print debug information into the graphml file
 2017-04-14 19:35:17 -07:00
Wesley W. Terpstra 7b8af96fc2 diplomacy: use circles for nodes again 2017-04-14 18:09:14 -07:00
Wesley W. Terpstra 2f22fca615 rocket: reverse input edge for better output 2017-04-14 18:09:14 -07:00
Wesley W. Terpstra ae8fd0c60f graphML: don't draw unconnected LazyModules 2017-04-14 18:09:14 -07:00
Wesley W. Terpstra fcf774f125 graphML: reverse interrupt arrows 2017-04-14 18:09:14 -07:00
Wesley W. TerpstraandGitHub 153178ac4f Merge pull request #678 from ucb-bar/rammodel-atomics 
RAMModel atomics
 2017-04-14 18:08:33 -07:00
Wesley W. Terpstra ba8be17c9a tilelink2: RAMModel, use CRC16 to check AMO response 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra 6aeec673f2 util: add a CRC calculator 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra d794218ec3 tilelink2: RAMModel now checks atomic results 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra 4f0ae1eab7 tilelink2: annotate which test generates RAMModel output 2017-04-14 15:13:40 -07:00
Wesley W. Terpstra 0b65fe9532 unittest: put AtomicAutomata under regression 2017-04-14 15:13:39 -07:00
Wesley W. Terpstra 248acbd1b4 tilelink2: add a generic TL2 atomic evaulation unit 2017-04-14 15:13:39 -07:00
Wesley W. TerpstraandGitHub 37c9ab3459 Merge pull request #671 from ucb-bar/cork-it 
Add a few diplomacy restrictions
 2017-04-11 15:55:37 -07:00
Wesley W. Terpstra 1c36ab8bf7 Fragmenter: forbid multiple sink IDs 
Otherwise a slave might respond with different IDs for different
requests and the Fragmenter would violate the requirement that
control signals remain unchanged for a burst.
 2017-04-11 12:38:00 -07:00
Wesley W. Terpstra 84dc2ae822 CacheCork: remove probe support 2017-04-11 12:34:18 -07:00
Wesley W. TerpstraandGitHub 71bf929505 maskgen: support wider granularity result (#665) 
Sometimes it is useful to generate a mask with bits that correspond
to a larger unit than bytes.
 2017-04-09 20:06:23 -07:00
Wesley W. TerpstraandAndrew Waterman 2f2b472098 rocket: split the interrupt controller into its own node 2017-03-30 00:36:23 -07:00