Merge pull request #777 from freechipsproject/print-axi-ids
coreplex: Improve memory map and AXI ID map output
This commit is contained in:
Wesley W. Terpstra
GitHub
commit
63b1f4f047
2
firrtl
2
firrtl
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@ -1 +1 @@
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Subproject commit 562806aa9e95c4095fcb38c5a34421b6ddc6d3fe
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Subproject commit d824c60c9643973e0ae9cddc5007b3d9592f8a52
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@ -115,22 +115,47 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
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val io: CoreplexNetworkBundle
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println("Generated Address Map")
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val ranges = outer.topManagers.get.flatMap { manager =>
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val prot = (if (manager.supportsGet) "R" else "") +
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(if (manager.supportsPutFull) "W" else "") +
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(if (manager.executable) "X" else "") +
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(if (manager.supportsAcquireB) " [C]" else "")
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AddressRange.fromSets(manager.address).map { r =>
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(manager.name, r.base, r.base+r.size, prot)
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private val aw = (outer.p(rocket.PAddrBits)-1)/4 + 1
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private val fmt = s"\t%${aw}x - %${aw}x %c%c%c%c %s"
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private def collect(path: List[String], value: ResourceValue): List[(String, ResourceAddress)] = {
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value match {
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case r: ResourceAddress => List((path(1), r))
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case ResourceMap(value, _) => value.toList.flatMap { case (key, seq) => seq.flatMap(r => collect(key :: path, r)) }
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case _ => Nil
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}
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}
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val aw = (outer.p(rocket.PAddrBits)-1)/4 + 1
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val nw = ranges.map(_._1.length).max
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val fmt = s"\t%${nw}s %${aw}x - %${aw}x, %s"
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ranges.sortWith(_._2 < _._2).foreach { case (name, start, end, prot) =>
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println(fmt.format(name, start, end, prot))
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private val ranges = collect(Nil, outer.bindingTree).groupBy(_._2).toList.flatMap { case (key, seq) =>
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AddressRange.fromSets(key.address).map { r => (r, key.r, key.w, key.x, key.c, seq.map(_._1)) }
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}.sortBy(_._1)
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private val json = ranges.map { case (range, r, w, x, c, names) =>
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println(fmt.format(
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range.base,
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range.base+range.size,
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if (r) 'R' else ' ',
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if (w) 'W' else ' ',
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if (x) 'X' else ' ',
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if (c) 'C' else ' ',
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names.mkString(", ")))
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s"""{"base":[${range.base}],"size":[${range.size}],"r":[$r],"w":[$w],"x":[$x],"c":[$c],"names":[${names.map('"'+_+'"').mkString(",")}]}"""
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}
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println("")
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ElaborationArtefacts.add("memmap.json", s"""{"mapping":[${json.mkString(",")}]}""")
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// Confirm that all of memory was described by DTS
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private val dtsRanges = AddressRange.unify(ranges.map(_._1))
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private val allRanges = AddressRange.unify(outer.topManagers.get.flatMap { m => AddressRange.fromSets(m.address) })
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if (dtsRanges != allRanges) {
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println("Address map described by DTS differs from physical implementation:")
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AddressRange.subtract(allRanges, dtsRanges).foreach { case r =>
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println(s"\texists, but undescribed by DTS: ${r}")
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}
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AddressRange.subtract(dtsRanges, allRanges).foreach { case r =>
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println(s"\tdoes not exist, but described by DTS: ${r}")
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}
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println("")
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}
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}
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/////
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@ -26,9 +26,9 @@ object JSON
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}
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private def helper(res: ResourceValue)(implicit path: Map[String, String]): Seq[String] = res match {
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case ResourceAddress(address, r, w, x) =>
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case ResourceAddress(address, r, w, x, c) =>
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AddressRange.fromSets(address).map { case AddressRange(base, size) =>
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s"""{"base":${base},"size":${size},"r":${r},"w":${w},"x":${x}}"""}
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s"""{"base":${base},"size":${size},"r":${r},"w":${w},"x":${x},"c":${c}}"""}
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case ResourceMapping(address, offset) =>
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AddressRange.fromSets(address).map { case AddressRange(base, size) =>
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s"""{"base":${base},"size":${size},"offset":${offset}}"""}
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@ -3,7 +3,6 @@
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package diplomacy
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import Chisel._
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import scala.math.max
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/** Options for memory regions */
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object RegionType {
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@ -110,6 +109,14 @@ case class AddressRange(base: BigInt, size: BigInt) extends Ordered[AddressRange
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Some(AddressRange(obase, oend-obase))
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}
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}
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private def helper(base: BigInt, end: BigInt) =
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if (base < end) Seq(AddressRange(base, end-base)) else Nil
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def subtract(x: AddressRange) =
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helper(base, end min x.base) ++ helper(base max x.end, end)
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// We always want to see things in hex
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override def toString() = "AddressRange(0x%x, 0x%x)".format(base, size)
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}
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// AddressSets specify the address space managed by the manager
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@ -197,6 +204,9 @@ object AddressRange
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}
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}.reverse
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}
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// Set subtraction... O(n*n) b/c I am lazy
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def subtract(from: Seq[AddressRange], take: Seq[AddressRange]): Seq[AddressRange] =
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take.foldLeft(from) { case (left, r) => left.flatMap { _.subtract(r) } }
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}
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object AddressSet
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@ -7,7 +7,7 @@ import config._
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import scala.collection.immutable.{ListMap,SortedMap}
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sealed trait ResourceValue
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final case class ResourceAddress(address: Seq[AddressSet], r: Boolean, w: Boolean, x: Boolean) extends ResourceValue
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final case class ResourceAddress(address: Seq[AddressSet], r: Boolean, w: Boolean, x: Boolean, c: Boolean) extends ResourceValue
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final case class ResourceMapping(address: Seq[AddressSet], offset: BigInt) extends ResourceValue
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final case class ResourceInt(value: BigInt) extends ResourceValue
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final case class ResourceString(value: String) extends ResourceValue
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@ -69,7 +69,7 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
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class GroundTestTile(implicit p: Parameters) extends LazyModule
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with HasGroundTestParameters {
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val slave = None
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val dcacheOpt = tileParams.dcache.map { dc => HellaCache(dc.nMSHRs == 0) }
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val dcacheOpt = tileParams.dcache.map { dc => HellaCache(0, dc.nMSHRs == 0) }
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val ucLegacy = LazyModule(new TLLegacy)
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val masterNode = TLOutputNode()
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@ -39,7 +39,7 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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}
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}
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class DCache(val scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) extends HellaCache()(p) {
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class DCache(hartid: Int, val scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) extends HellaCache(hartid)(p) {
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override lazy val module = new DCacheModule(this)
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}
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@ -147,20 +147,23 @@ class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
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/** Base classes for Diplomatic TL2 HellaCaches */
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abstract class HellaCache(implicit p: Parameters) extends LazyModule {
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abstract class HellaCache(hartid: Int)(implicit p: Parameters) extends LazyModule {
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private val cfg = p(TileKey).dcache.get
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val firstMMIO = max(1, cfg.nMSHRs)
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val node = TLClientNode(Seq(TLClientPortParameters(
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clients = cfg.scratch.map { _ => Seq(
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TLClientParameters(
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name = s"Core ${hartid} DCache MMIO",
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sourceId = IdRange(0, cfg.nMMIOs),
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requestFifo = true))
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} getOrElse { Seq(
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TLClientParameters(
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name = s"Core ${hartid} DCache",
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sourceId = IdRange(0, firstMMIO),
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supportsProbe = TransferSizes(1, cfg.blockBytes)),
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TLClientParameters(
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name = s"Core ${hartid} DCache MMIO",
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sourceId = IdRange(firstMMIO, firstMMIO+cfg.nMMIOs),
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requestFifo = true))
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},
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@ -186,9 +189,9 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
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}
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object HellaCache {
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def apply(blocking: Boolean, scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) = {
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if (blocking) LazyModule(new DCache(scratch))
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else LazyModule(new NonBlockingDCache)
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def apply(hartid: Int, blocking: Boolean, scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) = {
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if (blocking) LazyModule(new DCache(hartid, scratch))
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else LazyModule(new NonBlockingDCache(hartid))
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}
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}
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@ -198,8 +201,9 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters {
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val module: HasHellaCacheModule
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implicit val p: Parameters
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def findScratchpadFromICache: Option[AddressSet]
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val hartid: Int
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var nDCachePorts = 0
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val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
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val dcache = HellaCache(hartid, tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
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tileBus.node := dcache.node
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}
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@ -36,7 +36,7 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
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class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends LazyModule
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with HasRocketCoreParameters {
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lazy val module = new ICacheModule(this)
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val masterNode = TLClientNode(TLClientParameters(sourceId = IdRange(0,1)))
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val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
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val icacheParams = tileParams.icache.get
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val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
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@ -660,7 +660,7 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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io.write.ready := Bool(true)
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}
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class NonBlockingDCache(implicit p: Parameters) extends HellaCache()(p) {
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class NonBlockingDCache(hartid: Int)(implicit p: Parameters) extends HellaCache(hartid)(p) {
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override lazy val module = new NonBlockingDCacheModule(this)
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}
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@ -241,7 +241,8 @@ trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
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private val config = p(ExtIn)
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val l2FrontendAXI4Node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
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masters = Seq(AXI4MasterParameters(
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id = IdRange(0, 1 << config.idBits))))))
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name = "AXI4 periphery",
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id = IdRange(0, 1 << config.idBits))))))
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private val fifoBits = 1
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fsb.node :=
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@ -311,6 +312,7 @@ trait PeripherySlaveTL extends HasTopLevelNetworks {
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private val config = p(ExtIn)
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val l2FrontendTLNode = TLBlindInputNode(Seq(TLClientPortParameters(
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clients = Seq(TLClientParameters(
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name = "TL periph",
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sourceId = IdRange(0, 1 << config.idBits))))))
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fsb.node :=
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@ -49,7 +49,9 @@ class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) ex
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require(totalSize % channels == 0)
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val node = AXI4BlindInputNode(Seq.fill(channels) {
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AXI4MasterPortParameters(Seq(AXI4MasterParameters(IdRange(0, 1 << config.idBits))))})
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AXI4MasterPortParameters(Seq(AXI4MasterParameters(
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name = "dut",
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id = IdRange(0, 1 << config.idBits))))})
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for (i <- 0 until channels) {
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val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
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@ -52,10 +52,8 @@ case class AHBSlavePortParameters(
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}
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case class AHBMasterParameters(
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name: String,
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nodePath: Seq[BaseNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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}
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case class AHBMasterPortParameters(
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masters: Seq[AHBMasterParameters])
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@ -11,7 +11,7 @@ import uncore.tilelink2._
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case class AHBToTLNode() extends MixedAdapterNode(AHBImp, TLImp)(
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dFn = { case AHBMasterPortParameters(masters) =>
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TLClientPortParameters(clients = masters.map { m =>
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TLClientParameters(nodePath = m.nodePath)
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TLClientParameters(name = m.name, nodePath = m.nodePath)
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})
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},
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uFn = { mp => AHBSlavePortParameters(
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@ -42,10 +42,8 @@ case class APBSlavePortParameters(
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}
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case class APBMasterParameters(
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name: String,
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nodePath: Seq[BaseNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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}
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case class APBMasterPortParameters(
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masters: Seq[APBMasterParameters])
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@ -16,15 +16,19 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
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masterFn = { mp =>
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// Create one new "master" per ID
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val masters = Array.tabulate(1 << idBits) { i => AXI4MasterParameters(
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name = "",
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id = IdRange(i, i+1),
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aligned = true,
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maxFlight = Some(0))
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}
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// Accumluate the names of masters we squish
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val names = Array.fill(1 << idBits) { new scala.collection.mutable.HashSet[String]() }
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// Squash the information from original masters into new ID masters
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mp.masters.foreach { m =>
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for (i <- m.id.start until m.id.end) {
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val j = i % (1 << idBits)
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val old = masters(j)
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names(j) += m.name
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masters(j) = old.copy(
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aligned = old.aligned && m.aligned,
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maxFlight = old.maxFlight.flatMap { o => m.maxFlight.map { n => o+n } })
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@ -32,7 +36,7 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
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}
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mp.copy(
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userBits = mp.userBits + max(0, log2Ceil(mp.endId) - idBits),
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masters = masters)
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masters = masters.zipWithIndex.map { case (m,i) => m.copy(name = names(i).toList.mkString(", "))})
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},
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slaveFn = { sp => sp
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})
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@ -58,12 +58,12 @@ case class AXI4SlavePortParameters(
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}
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case class AXI4MasterParameters(
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name: String,
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id: IdRange = IdRange(0, 1),
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aligned: Boolean = false,
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maxFlight: Option[Int] = None, // None = infinite, else is a per-ID cap
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nodePath: Seq[BaseNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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maxFlight.foreach { m => require (m >= 0) }
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}
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@ -13,9 +13,10 @@ case class AXI4ToTLNode() extends MixedAdapterNode(AXI4Imp, TLImp)(
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masters.foreach { m => require (m.maxFlight.isDefined, "AXI4 must include a transaction maximum per ID to convert to TL") }
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val maxFlight = masters.map(_.maxFlight.get).max
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TLClientPortParameters(
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clients = masters.flatMap { m =>
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clients = masters.filter(_.maxFlight != Some(0)).flatMap { m =>
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for (id <- m.id.start until m.id.end)
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yield TLClientParameters(
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name = s"${m.name} ID#${id}",
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sourceId = IdRange(id * maxFlight*2, (id+1) * maxFlight*2), // R+W ids are distinct
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nodePath = m.nodePath,
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requestFifo = true)
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@ -1093,7 +1093,7 @@ class ClockedDMIIO(implicit val p: Parameters) extends ParameterizedBundle()(p){
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class DMIToTL(implicit p: Parameters) extends LazyModule {
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val node = TLClientNode(TLClientParameters())
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val node = TLClientNode(TLClientParameters("debug"))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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@ -15,6 +15,7 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
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val node = TLAdapterNode(
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clientFn = { cp =>
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cp.copy(clients = Seq(TLClientParameters(
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name = "TLBroadcast",
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sourceId = IdRange(0, 1 << log2Ceil(cp.endSourceId*4)))))
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},
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managerFn = { mp =>
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@ -46,7 +46,8 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
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// We require that all the responses are mutually FIFO
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// Thus we need to compact all of the masters into one big master
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clientFn = { c => c.copy(clients = Seq(TLClientParameters(
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sourceId = IdRange(0, c.endSourceId << addedBits),
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name = "TLFragmenter",
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sourceId = IdRange(0, c.endSourceId << addedBits),
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requestFifo = true))) },
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managerFn = { m => m.copy(managers = m.managers.map(mapManager)) })
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@ -85,7 +85,9 @@ class TLFuzzer(
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noModify: Boolean = false,
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overrideAddress: Option[AddressSet] = None)(implicit p: Parameters) extends LazyModule
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{
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val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,inFlight)))
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val node = TLClientNode(TLClientParameters(
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name = "Fuzzer",
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sourceId = IdRange(0,inFlight)))
|
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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@ -12,6 +12,7 @@ class TLLegacy(implicit p: Parameters) extends LazyModule with HasTileLinkParame
|
|||
{
|
||||
// TL legacy clients don't support anything fancy
|
||||
val node = TLClientNode(TLClientParameters(
|
||||
name = "TLLegacy",
|
||||
sourceId = IdRange(0, 1 << tlClientXactIdBits)))
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with HasTileLinkParameters {
|
||||
|
|
|
|||
|
|
@ -60,7 +60,8 @@ case class TLManagerParameters(
|
|||
ResourceAddress(address,
|
||||
r = supportsAcquireB || supportsGet,
|
||||
w = supportsAcquireT || supportsPutFull,
|
||||
x = executable)
|
||||
x = executable,
|
||||
c = supportsAcquireB)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -166,6 +167,7 @@ case class TLManagerPortParameters(
|
|||
}
|
||||
|
||||
case class TLClientParameters(
|
||||
name: String,
|
||||
sourceId: IdRange = IdRange(0,1),
|
||||
nodePath: Seq[BaseNode] = Seq(),
|
||||
requestFifo: Boolean = false, // only a request, not a requirement
|
||||
|
|
@ -196,8 +198,6 @@ case class TLClientParameters(
|
|||
supportsGet.max,
|
||||
supportsPutFull.max,
|
||||
supportsPutPartial.max).max
|
||||
|
||||
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
|
||||
}
|
||||
|
||||
case class TLClientPortParameters(
|
||||
|
|
|
|||
|
|
@ -14,7 +14,9 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod
|
|||
require (maxInFlight > 0)
|
||||
|
||||
// The SourceShrinker completely destroys all FIFO property guarantees
|
||||
private val client = TLClientParameters(sourceId = IdRange(0, maxInFlight))
|
||||
private val client = TLClientParameters(
|
||||
name = "TLSourceShrinker",
|
||||
sourceId = IdRange(0, maxInFlight))
|
||||
val node = TLAdapterNode(
|
||||
// We erase all client information since we crush the source Ids
|
||||
clientFn = { _ => TLClientPortParameters(clients = Seq(client)) },
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ import AHBParameters._
|
|||
|
||||
case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
|
||||
dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) =>
|
||||
val masters = clients.map { case c => AHBMasterParameters(nodePath = c.nodePath) }
|
||||
val masters = clients.map { case c => AHBMasterParameters(name = c.name, nodePath = c.nodePath) }
|
||||
AHBMasterPortParameters(masters)
|
||||
},
|
||||
uFn = { case AHBSlavePortParameters(slaves, beatBytes) =>
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ import APBParameters._
|
|||
|
||||
case class TLToAPBNode() extends MixedAdapterNode(TLImp, APBImp)(
|
||||
dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) =>
|
||||
val masters = clients.map { case c => APBMasterParameters(nodePath = c.nodePath) }
|
||||
val masters = clients.map { case c => APBMasterParameters(name = c.name, nodePath = c.nodePath) }
|
||||
APBMasterPortParameters(masters)
|
||||
},
|
||||
uFn = { case APBSlavePortParameters(slaves, beatBytes) =>
|
||||
|
|
|
|||
|
|
@ -6,16 +6,18 @@ import Chisel._
|
|||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import util.PositionalMultiQueue
|
||||
import util.ElaborationArtefacts
|
||||
import uncore.axi4._
|
||||
import scala.math.{min, max}
|
||||
|
||||
case class TLToAXI4Node(beatBytes: Int) extends MixedAdapterNode(TLImp, AXI4Imp)(
|
||||
dFn = { p =>
|
||||
val idSize = p.clients.map { c => if (c.requestFifo) 1 else c.sourceId.size }
|
||||
val clients = p.clients.sortWith(TLToAXI4.sortByType _)
|
||||
val idSize = clients.map { c => if (c.requestFifo) 1 else c.sourceId.size }
|
||||
val idStart = idSize.scanLeft(0)(_+_).init
|
||||
val masters = ((idStart zip idSize) zip p.clients) map { case ((start, size), c) =>
|
||||
val masters = ((idStart zip idSize) zip clients) map { case ((start, size), c) =>
|
||||
AXI4MasterParameters(
|
||||
name = c.name,
|
||||
id = IdRange(start, start+size),
|
||||
aligned = true,
|
||||
maxFlight = Some(if (c.requestFifo) c.sourceId.size else 1),
|
||||
|
|
@ -41,7 +43,7 @@ case class TLToAXI4Node(beatBytes: Int) extends MixedAdapterNode(TLImp, AXI4Imp)
|
|||
minLatency = p.minLatency)
|
||||
})
|
||||
|
||||
class TLToAXI4(beatBytes: Int, combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
|
||||
class TLToAXI4(beatBytes: Int, combinational: Boolean = true, adapterName: Option[String] = None)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLToAXI4Node(beatBytes)
|
||||
|
||||
|
|
@ -58,15 +60,29 @@ class TLToAXI4(beatBytes: Int, combinational: Boolean = true)(implicit p: Parame
|
|||
require (slaves(0).interleavedId.isDefined)
|
||||
slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) }
|
||||
|
||||
val axiDigits = String.valueOf(edgeOut.master.endId-1).length()
|
||||
val tlDigits = String.valueOf(edgeIn.client.endSourceId-1).length()
|
||||
|
||||
// Construct the source=>ID mapping table
|
||||
adapterName.foreach { n => println(s"$n AXI4-ID <= TL-Source mapping:") }
|
||||
val idTable = Wire(Vec(edgeIn.client.endSourceId, out.aw.bits.id))
|
||||
var idCount = Array.fill(edgeOut.master.endId) { 0 }
|
||||
(edgeIn.client.clients zip edgeOut.master.masters) foreach { case (c, m) =>
|
||||
val maps = (edgeIn.client.clients.sortWith(TLToAXI4.sortByType) zip edgeOut.master.masters) flatMap { case (c, m) =>
|
||||
for (i <- 0 until c.sourceId.size) {
|
||||
val id = m.id.start + (if (c.requestFifo) 0 else i)
|
||||
idTable(c.sourceId.start + i) := UInt(id)
|
||||
idCount(id) = idCount(id) + 1
|
||||
}
|
||||
adapterName.map { n =>
|
||||
val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s"
|
||||
println(fmt.format(m.id.start, m.id.end, c.sourceId.start, c.sourceId.end, c.name, if (c.supportsProbe) " CACHE" else ""))
|
||||
s"""{"axi4-id":[${m.id.start},${m.id.end}],"tilelink-id":[${c.sourceId.start},${c.sourceId.end}],"master":["${c.name}"],"cache":[${!(!c.supportsProbe)}]}"""
|
||||
}
|
||||
}
|
||||
|
||||
adapterName.foreach { n =>
|
||||
println("")
|
||||
ElaborationArtefacts.add(s"${n}.axi4.json", s"""{"mapping":[${maps.mkString(",")}]}""")
|
||||
}
|
||||
|
||||
// We need to keep the following state from A => D: (addr_lo, size, source)
|
||||
|
|
@ -203,9 +219,17 @@ class TLToAXI4(beatBytes: Int, combinational: Boolean = true)(implicit p: Parame
|
|||
object TLToAXI4
|
||||
{
|
||||
// applied to the TL source node; y.node := TLToAXI4(beatBytes)(x.node)
|
||||
def apply(beatBytes: Int, combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
|
||||
val axi4 = LazyModule(new TLToAXI4(beatBytes, combinational))
|
||||
def apply(beatBytes: Int, combinational: Boolean = true, adapterName: Option[String] = None)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
|
||||
val axi4 = LazyModule(new TLToAXI4(beatBytes, combinational, adapterName))
|
||||
axi4.node := x
|
||||
axi4.node
|
||||
}
|
||||
|
||||
def sortByType(a: TLClientParameters, b: TLClientParameters): Boolean = {
|
||||
if ( a.supportsProbe && !b.supportsProbe) return false
|
||||
if (!a.supportsProbe && b.supportsProbe) return true
|
||||
if ( a.requestFifo && !b.requestFifo ) return false
|
||||
if (!a.requestFifo && b.requestFifo ) return true
|
||||
return false
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit p:
|
|||
// Find a good mask for address decoding
|
||||
val port_addrs = node.edgesOut.map(_.manager.managers.map(_.address).flatten)
|
||||
val routingMask = AddressDecoder(port_addrs)
|
||||
val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct)
|
||||
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
|
||||
val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
|
||||
|
||||
// Print the mapping
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user