riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman 568bfa6c50 Purge legacy HTIF things 
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
 2016-06-23 13:23:57 -07:00
Andrew Waterman 2d44be747a Fix groundtest without HTIF 2016-06-23 12:17:26 -07:00
Andrew Waterman 30331fcaeb Remove HTIF; use debug module for testing in simulation 2016-06-23 00:32:05 -07:00
Andrew Waterman 4a8e6c773a Fix +verbose flag for verilator 2016-06-17 21:09:08 -07:00
Andrew Waterman b79db89c03 Update breakpoint spec 2016-06-09 19:13:55 -07:00
Andrew Waterman 9e86b9efc9 Add provisional breakpoint support 2016-06-08 22:34:19 -07:00
Andrew Waterman 2c17f828b6 bump chisel and rocket 2016-06-06 21:36:51 -07:00
Andrew Waterman 1311e78d3f Add blocking D$ flush support 2016-05-31 19:28:41 -07:00
Andrew Waterman 44a216038f Use more generic TileLinkWidthAdapter 2016-05-27 13:38:13 -07:00
Andrew Waterman 10f0e13c25 Use more parsimonious queue depths 2016-05-26 18:04:22 -07:00
Andrew Waterman 3cc236e9c4 By default, use same TileLink width everywhere 
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
 2016-05-26 18:04:01 -07:00
Andrew Waterman ec0d178010 Support M-mode-only implementations 2016-05-25 15:40:53 -07:00
Andrew Waterman da105a5944 Don't allow travis to recurse through submodules 2016-05-25 13:27:49 -07:00
Andrew Waterman e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Andrew Waterman a8462d3cfc bump chisel 2016-05-25 11:09:50 -07:00
Andrew Waterman 684d902059 Fix PLIC instantiation when S-mode is disabled 2016-05-13 11:22:46 -07:00
Andrew Waterman 6aa708bcee Disable MMIO by default to avoid disconnected nets 2016-05-11 13:12:39 -07:00
Andrew Waterman fbff46d27d bump rocket 2016-05-10 10:57:03 -07:00
Andrew Waterman aac89ca1f0 Add PLIC 2016-05-10 00:27:31 -07:00
Andrew WatermanandHoward Mao 8b06947446 Run bmarks faster (hopefully) 2016-05-04 22:47:34 -07:00
Andrew Waterman 15f4af19cf Remove HTIF CPU port 2016-05-03 13:55:59 -07:00
Andrew Waterman c7c8ae5468 Instantiate PRCI block 2016-05-02 18:08:33 -07:00
Andrew Waterman 6d1e82bddf Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port 2016-05-02 15:21:55 -07:00
Andrew Waterman c4d2d29e80 Stub out debug module, rather than leaving it floating 2016-04-30 22:37:39 -07:00
Andrew Waterman 46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
Andrew Waterman d0aa4c722d More WIP on new memory map 2016-04-28 16:15:31 -07:00
Andrew Waterman 1f211b37df WIP on new memory map 2016-04-27 14:57:54 -07:00
Andrew WatermanandHenry Cook c4c6bd1040 Bump rocket. 
Closes #84.
 2016-04-01 18:20:32 -07:00
Andrew WatermanandHenry Cook b43a85e2e8 Make ExampleSmallConfig/DefaultRV32Config smaller 2016-04-01 18:18:08 -07:00
Andrew WatermanandHenry Cook 6878e3265f Default RowBits to TileLink width, not XLen 2016-04-01 18:18:08 -07:00
Andrew WatermanandHenry Cook 46d7dceb1e Disable printf/assert during reset 2016-04-01 18:18:08 -07:00
Andrew WatermanandHenry Cook cd9e07d8e7 Update sbt to 0.13.11 2016-04-01 18:18:08 -07:00
Andrew WatermanandHenry Cook bd3dba7f66 Fix LR/SC livelock bug 
Closes #74.
 2016-04-01 18:18:08 -07:00
Andrew Waterman 6c48dc3471 Use more sensible knob values for SmallConfig 2016-03-25 14:18:24 -07:00
Andrew Waterman cce89f5fbc Bump rocket 2016-03-25 14:18:15 -07:00
Andrew Waterman 9dc0cbdfa4 WIP on privileged spec v1.9 2016-03-14 18:03:33 -07:00
Andrew Waterman 25091003af Add RV32 test/configuration options 
These won't actually work until further commits.  Rocket RV32 support
is complete, but on the priv-1.9 branch.
 2016-03-10 17:40:21 -08:00
Andrew Waterman 7a75a03123 tabs are evil 2016-03-10 14:18:56 -08:00
Andrew Waterman fdd19145e9 bump chisel/hardfloat/junctions/uncore submodules 2016-01-17 01:50:04 -08:00
Andrew Waterman fc638c6339 Chisel3 compatibility fixes 2016-01-12 16:28:05 -08:00
Andrew Waterman 603db5e271 Chisel3 compatibility; new NaNs; new MIPI behavior 2016-01-12 16:25:03 -08:00
Andrew Waterman e0d849fec5 Fix zscale testing 
Use the following command in vsim:

make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
 2015-12-01 17:31:48 -08:00
Andrew Waterman 5eeb8969f6 fix zscale build (run still fails) 2015-12-01 16:20:34 -08:00
Andrew Waterman e25a020e60 Construct device tree ROM in MMIO region 
Rebuild riscv-tools for this to work!
 2015-11-25 21:23:37 -08:00
Andrew Waterman 49d93da87e Factor out more common zscale code 2015-11-24 19:17:21 -08:00
Andrew Waterman 52b25c3da0 Factor out more common zscale code 2015-11-24 18:34:03 -08:00
Andrew Waterman 1761db3272 Factor out some common code from zscale 2015-11-24 18:14:06 -08:00
Andrew Waterman 5195a5b891 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:53:14 -08:00
Andrew Waterman c2ad0b7dd4 Unfuck fpga-zynq submodule pointer 
Sorry, Scott.
 2015-10-01 15:00:35 -07:00
Andrew Waterman 996670a4a6 Point to correct Chisel commit 2015-10-01 10:31:29 -07:00
Andrew Waterman 8da7be3211 More Chisel3 compatibility fixes 2015-09-30 14:37:40 -07:00
Andrew Waterman 79cdf6efc0 Make perf counters optional 2015-09-28 13:56:08 -07:00
Andrew Waterman c6bcc832a1 Chisel3: Don't use Vec.fill for IOs 2015-09-20 13:43:56 -07:00
Andrew Waterman fd58c52250 Update to latest chisel 2015-09-20 13:37:53 -07:00
Andrew Waterman 9b038db34a Upgrade scala to 2.11.6 2015-08-05 15:37:03 -07:00
Andrew Waterman 700910adff Chisel3 compatibility fix for <> 2015-08-05 15:34:40 -07:00
Andrew Waterman 34b9a7fdc5 Various Chisel3 compatibility changes 2015-08-03 18:54:56 -07:00
Andrew Waterman b7d7ced41b Update to new ISA 2013-09-21 06:40:23 -07:00
Andrew Waterman 42970c9a99 Update Rocket 2013-09-15 04:39:52 -07:00
Andrew Waterman 628745226c Use spike disassembler riscv-dis if it exists 2013-09-15 04:25:53 -07:00
Andrew Waterman 80003b3019 Support RoCC 2013-09-15 04:25:26 -07:00
Andrew Waterman fbdbb01232 update to new isa; disable vector tests 2013-09-12 17:04:03 -07:00
Andrew Waterman c5f01f3f87 update rocket 2013-06-15 00:55:34 -07:00
Andrew Waterman 4ae0c68303 require -std=c++11, as -std=c++0x doesn't cut it 2013-06-14 00:28:42 -07:00
Andrew Waterman ae0716fb6d Use chisel printf for logging 2013-06-13 10:53:23 -07:00
Andrew Waterman e8fcdb56a6 update chisel to work around xilinx ise bug 2013-05-03 01:47:15 -07:00
Andrew Waterman d825c9d6e9 make fpga Makefile work with updated Makefrag 2013-05-02 05:09:45 -07:00
Andrew Waterman cfa86dba4f add FPGA test bench 
The memory models now support back pressure on the response.
 2013-05-02 04:59:32 -07:00
Andrew Waterman d2e1828714 gracefully kill htif thread, fixing tty stuff 2013-05-02 04:59:32 -07:00
Andrew Waterman 50bd9a08a7 resynchronize fpga uncore 2013-05-01 01:12:47 -07:00
Andrew Waterman 7f5282d355 replace RDNPC with AUIPC 2013-04-22 04:21:46 -07:00
Andrew Waterman 7ea782fd22 add LR/SC 2013-04-07 19:36:15 -07:00
Andrew Waterman def11e44b8 don't pipe stdout to vcd2vpd 2013-03-25 17:01:13 -07:00
Andrew Waterman ef4927c9ad use a named pipe for VCD -> VPD conversion 2013-03-25 16:19:19 -07:00
Andrew Waterman c6695bee7c fix emulator HTIF interface bug 2013-02-20 16:11:21 -08:00
Andrew Waterman fc26150933 update to new Mem style 2013-02-20 16:10:47 -08:00
Andrew Waterman dbb61306f0 randomize coreid mapping 2013-01-26 16:13:14 -08:00
Andrew Waterman 4077b22929 include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00