riscv/rocket-chip
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add LR/SC

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Andrew Waterman committed 2013-04-07 19:36:15 -07:00
1 parent c6b56c5f25
commit 7ea782fd22
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Makefrag
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@@ -20,6 +20,7 @@ libdramsim.a: $(DRAMSIM_OBJS)
global_tstdir = $(basedir)/riscv-asmtests-bmarks/riscv-tests
global_asm_tests = \
riscv_ipi \
riscv_lrsc \
riscv_add \
riscv_addi \
riscv_amoadd_d \
riscv-rocket
+1 -1
Submodule riscv-rocket updated: b9e6abf3de...31a4ad984c.
uncore
+1 -1
Submodule uncore updated: 1f89e568ac...ccc4badd15.