add LR/SC
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1
Makefrag
1
Makefrag
@ -20,6 +20,7 @@ libdramsim.a: $(DRAMSIM_OBJS)
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global_tstdir = $(basedir)/riscv-asmtests-bmarks/riscv-tests
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global_asm_tests = \
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riscv_ipi \
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riscv_lrsc \
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riscv_add \
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riscv_addi \
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riscv_amoadd_d \
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@ -1 +1 @@
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Subproject commit b9e6abf3defd2c54a990dfca0417bfc704fefd3d
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Subproject commit 31a4ad984cffb3c441e4b30a4c9060743f3295a8
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2
uncore
2
uncore
@ -1 +1 @@
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Subproject commit 1f89e568acf9bed6a1d4ccf1c96ae79370a58225
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Subproject commit ccc4badd15c6f88a4af5d97e8c0fcd105baf43fa
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