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Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
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Andrew Waterman cfa86dba4f add FPGA test bench 
The memory models now support back pressure on the response.
2013-05-02 04:59:32 -07:00
chisel@b5b72e5b98 update to new Mem style 2013-02-20 16:10:47 -08:00
csrc add FPGA test bench 2013-05-02 04:59:32 -07:00
dramsim2@0b3ee6799a integrate updated rocket/uncore 2012-10-18 17:51:41 -07:00
emulator commit awesome vlsi/energy scripts 2013-05-01 02:59:11 -07:00
hardfloat@fc09bea899 upgrade to new rocket; improve vlsi makefiles 2012-11-17 07:21:29 -08:00
project print stack trace if elaboration fails 2012-11-20 05:39:48 -08:00
riscv-rocket@a5063baf1a add FPGA test bench 2013-05-02 04:59:32 -07:00
riscv-tests@1dd1e13180 add FPGA test bench 2013-05-02 04:59:32 -07:00
src/main/scala add FPGA test bench 2013-05-02 04:59:32 -07:00
uncore@d154f3fdb6 add FPGA test bench 2013-05-02 04:59:32 -07:00
.gitmodules Added dramsim2 memory model to the emulator backend 2012-10-14 14:06:28 -07:00
Makefrag commit awesome vlsi/energy scripts 2013-05-01 02:59:11 -07:00
README update README 2013-04-24 02:05:28 -07:00
sbt-launch.jar everything to get emulator working 2012-10-01 19:30:11 -07:00

README 

Quick and dirty instructions:

CHECKOUT THE CODE:

  git submodule init
  git submodule update

  cd riscv-gcc-isasim
  git submodule init
  git submodule update


BUILDING THE TOOLCHAIN:

  To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain:

    export RISCV=/path/to/riscv/toolchain/installation
    cd riscv-gcc-isasim
    ./build.sh

  To build asm tests and benchmarks (you must have the RISC-V toolchain installed and in your path):

    cd riscv-tests/isa/
    make -j

    cd riscv-asmtests-bmarks/riscv-bmarks/
    make -j

BUILDING THE PROJECT:

  To build the C simulator:

    cd emulator
    make

  To build the VCS simulator:

    cd vlsi/build/vcs-sim-rtl
    make

  in either case, you can run a set of assembly tests or simple benchmarks:

    make run-asm-tests
    make run-vecasm-tests
    make run-vecasm-timer-tests
    make run-bmarks-test

  To build a C simulator that is capable of VCD waveform generation:

    cd emulator
    make emulator-debug

  And to run the assembly tests on the C simulator and generate waveforms:

    make run-asm-tests-debug
    make run-vecasm-tests-debug
    make run-vecasm-timer-tests-debug
    make run-bmarks-test-debug


UPDATING TO A NEWER VERSION OF CHISEL:

  To grab a newer version of chisel:

    git submodule init
    git submodule update
    cd chisel
    git pull origin master

  Then, to compile it and install it into the rocket repo:

    cd sbt
    sbt package
    cp chisel/target/scala-2.8.1/chisel_2.8.1-1.1.jar ../../sbt/work/lib

  If you commit a new jar, you must also commit the updated chisel submodule.