1
0
Go to file
2013-01-24 23:57:23 -08:00
chisel@c363ff20e6 include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
csrc include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
dramsim2@0b3ee6799a integrate updated rocket/uncore 2012-10-18 17:51:41 -07:00
emulator include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
hardfloat@fc09bea899 upgrade to new rocket; improve vlsi makefiles 2012-11-17 07:21:29 -08:00
project print stack trace if elaboration fails 2012-11-20 05:39:48 -08:00
riscv-rocket@2a91f23857 include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
src/main/scala include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
uncore@871f7a86bc include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
.gitmodules Added dramsim2 memory model to the emulator backend 2012-10-14 14:06:28 -07:00
Makefrag simplify c++ memory models; support +dramsim flag 2012-12-04 07:04:26 -08:00
README directly integrate dramsim build 2012-10-18 18:59:37 -07:00
sbt-launch.jar everything to get emulator working 2012-10-01 19:30:11 -07:00

Quick and dirty instructions:

CHECKOUT THE CODE:

  git submodule init
  git submodule update

  cd riscv-gcc-isasim
  git submodule init
  git submodule update


BUILDING THE TOOLCHAIN:

  To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain:

    cd riscv-gcc-isasim
    vi build.sh (Edit INSTALL_PREFIX)
    ./build.sh

  To build asm tests and benchmarks (you must have the RISC-V toolchain installed and in your path):

    cd riscv-asmtests-bmarks/riscv-tests/
    make

    cd riscv-asmtests-bmarks/riscv-bmarks/
    make

BUILDING THE PROJECT:

  To build the C simulator:

    cd emulator
    make

  To build the VCS simulator:

    cd vlsi/build/vcs-sim-rtl
    make

  in either case, you can run a set of assembly tests or simple benchmarks:

    make run-asm-tests
    make run-vecasm-tests
    make run-vecasm-timer-tests
    make run-bmarks-test

  To build a C simulator that is capable of VCD waveform generation:

    cd emulator
    make emulator-debug

  And to run the assembly tests on the C simulator and generate waveforms:

    make run-asm-tests-debug
    make run-vecasm-tests-debug
    make run-vecasm-timer-tests-debug
    make run-bmarks-test-debug


UPDATING TO A NEWER VERSION OF CHISEL:

  To grab a newer version of chisel:

    git submodule init
    git submodule update
    cd chisel
    git pull origin master

  Then, to compile it and install it into the rocket repo:

    cd sbt
    sbt package
    cp chisel/target/scala-2.8.1/chisel_2.8.1-1.1.jar ../../sbt/work/lib

  If you commit a new jar, you must also commit the updated chisel submodule.