546205b174
Chisel3 compatibility: use >>Int instead of >>UInt
2015-08-05 15:29:03 -07:00
fb5524372d
bump scala to 2.11.6
2015-08-03 19:51:08 -07:00
d4c94c6566
Chisel3 has different Vec semantics
...
Vec(a, b) := c doesn't modify a and b in chisel3.
2015-08-03 19:08:00 -07:00
c345d72af4
Chisel3: Flip order of := and <>
2015-08-03 18:53:09 -07:00
ef319edc84
Bits -> UInt
2015-08-02 21:03:42 -07:00
52fc34a138
Chisel3: bulk connect is not commutative
...
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with. Should make
for lively debate.
2015-08-01 21:11:25 -07:00
6c0e1e33ab
Purge UInt := SInt assignments
2015-07-31 15:42:10 -07:00
6d7cc37e87
Specify some uninferrable widths
...
It's really scary that Chisel2 passed this stuff.
2015-07-31 14:23:52 -07:00
45cf64dbd7
Use UInt instead of Vec[Bool]
2015-07-31 04:59:45 -07:00
57930e8a26
Chisel3 compatibility potpourri
2015-07-30 23:53:02 -07:00
db7258f887
Add junctions to the possible managed dependency list.
2015-07-30 15:11:23 -07:00
d2a594fb57
new junctions repo has mem size constants
2015-07-29 18:05:54 -07:00
9d67ef4ee2
simplify .sbt files
2015-07-29 17:22:33 -07:00
ce161b83e3
Chisel3 compatibility: avoid subword assignment
2015-07-29 15:03:13 -07:00
c8c312e860
minor btb cleanup
2015-07-29 15:03:01 -07:00
a2fdcdcaef
Use Seq, not Iterable, when traversal order matters
2015-07-29 00:24:58 -07:00
431dd2219b
Another Bits -> BitPat
2015-07-28 20:13:56 -07:00
049fc8dc24
Chisel3 compatibility: use BitPat for don't-cares
...
This one's hella ugly, but for the time being, idgaf.
2015-07-28 02:48:49 -07:00
f2dcc40e67
Chisel3 compatibility changes
2015-07-27 12:42:20 -07:00
ae73e3a997
Only instantiate div/sqrt unit if requested
2015-07-22 22:18:18 -07:00
e9433ee01e
Minor cleanup
2015-07-22 17:38:08 -07:00
b4e4ceed3d
Factor out some more hazard detection code
2015-07-22 15:52:13 -07:00
bd785e7d19
Factor out common hazard detection code
2015-07-22 15:46:20 -07:00
cc447c8110
Refactor pipeline RTL (merge ctrl + dpath into rocket)
2015-07-21 17:10:56 -07:00
ac6e73e317
Add Wire() wrap
2015-07-15 20:24:18 -07:00
5b7f3c3006
Don't use clone
2015-07-15 17:30:50 -07:00
be2ff6dec7
Vec(Reg) -> Reg(Vec)
2015-07-15 12:33:46 -07:00
a78e28523c
Chisel3: Don't mix Mux types
2015-07-11 14:06:08 -07:00
3233867390
Use Chisel3 SeqMem construct
2015-07-11 13:34:57 -07:00
5ed2899e56
Merge pull request #10 from wsong83/fix
...
L1 D$ writeback unit, reduce re-read data array
2015-07-06 15:18:49 -07:00
5362e2bbbd
New machine-mode timer facility
2015-07-05 16:38:49 -07:00
5e009ecc75
Fix an apparently benign PC sign-extension bug
2015-06-11 16:08:39 -07:00
4db60d9e9d
code clean in dcache, no need to check the condition twice.
2015-06-02 22:06:12 +01:00
b6e68773fd
nbdcache, writeback unit: when release is not ready and data is not ready for a beat too, no need to re-read data array.
2015-05-30 16:25:27 +01:00
6a9390c50e
Avoid spurious D$ assertion failures
...
For the Rocket pipeline, this fix is needless and the problem is that the
assertion is too conservative, but I solved it this way to avoid problems
for other plausible use cases where physical and virtual accesses are
intermixed.
2015-05-19 03:00:53 -07:00
f460cb6c54
Update to privileged architecture 1.7
2015-05-19 02:32:21 -07:00
254498042a
Fix Split for 0-width wires
2015-05-18 18:23:17 -07:00
d31b26c342
Clean up handling of icache's io.cpu.npc signal
2015-05-18 18:22:48 -07:00
b09832f1b5
ICache now returns the "next PC" signal.
...
useful for other modules that need access to the fetch PC on the
cycle it is sent to the SRAM.
2015-05-07 04:53:05 -07:00
a315fe93c1
simplify ClientMetadata.makeRelease
2015-04-20 10:46:24 -07:00
3048f4785a
HeaderlessTileLinkIO -> ClientTileLinkIO
2015-04-17 16:56:53 -07:00
49f1c0aa7b
moved ecc lib to uncore
2015-04-13 15:58:10 -07:00
91e882e3f8
Use HeaderlessTileLinkIO
2015-04-13 15:58:10 -07:00
517d0d4b89
feedback on PR
2015-04-12 18:44:03 -07:00
4d6ebded02
Added assert to nbdcache
2015-04-11 02:58:34 -07:00
a564f08702
Rename dmem.sret signal to more accurate invalidate_lr
2015-04-11 02:26:33 -07:00
8fc2d38ca9
Removed unnecessary signal in CSRIO
2015-04-11 02:20:34 -07:00
2f88c5ca9d
Renamed PCR to CSR
2015-04-11 02:16:44 -07:00
11dbd4221a
Fixed front-end to support four-wide fetch.
2015-04-10 17:53:47 -07:00
9ade0e41cc
Integrate divide/sqrt unit
2015-04-04 16:39:17 -07:00
