Howard Mao
d12403e7dc
fix up and simplify TL -> NASTI converter logic
2015-10-19 13:47:13 -07:00
Colin Schmidt
2cee8c8bec
Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port
2015-10-18 13:09:17 -07:00
Henry Cook
8c3370c2e3
L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale)
2015-10-16 19:15:47 -07:00
Henry Cook
6f8997bee9
Minor refactor of StoreGen/AMOALU.
2015-10-16 19:12:46 -07:00
Henry Cook
1441590c3b
add enabled field to BTBParameters
2015-10-16 19:12:39 -07:00
Henry Cook
d391f97953
Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU.
2015-10-16 19:11:06 -07:00
Henry Cook
e1f573918d
simplify TileLinkParameters with Option
2015-10-16 18:24:38 -07:00
Howard Mao
49667aa4b0
make sure broadcast acquire tracker doesn't try to send requests back-to-back
2015-10-14 18:56:13 -07:00
Howard Mao
c4117eb9a2
make sure TL parameters change properly throughout
...
* Outermost TL parameters should have the width set to be the same as the
MIF data width.
* Broadcast Hub and Narrower, which use different sets of TL parameters
should use the proper set of parameters at each interface
2015-10-14 18:03:39 -07:00
Howard Mao
1d362d6d3a
make sure correct parameters are used for TileLink constructors
2015-10-14 17:58:54 -07:00
Henry Cook
969ecaecf8
pass parameters to BuildRoCC
2015-10-14 14:16:47 -07:00
Henry Cook
4270fd78a5
Merge branch 'param-refactor-tl'
2015-10-14 12:16:22 -07:00
Henry Cook
68cb54bc68
refactor tilelink params
2015-10-14 12:14:36 -07:00
Henry Cook
7fa3eb95e3
refactor tilelink params
2015-10-14 12:13:37 -07:00
Henry Cook
66ea39638e
GlobalAddrMap
2015-10-14 00:23:28 -07:00
Henry Cook
31be6407ec
Removed all traces of params
2015-10-14 00:23:28 -07:00
Henry Cook
908922c1a4
refactor NASTI to not use param
2015-10-14 00:23:28 -07:00
Henry Cook
da5fe84f53
Merge branch 'param-refactor'
2015-10-14 00:14:13 -07:00
Henry Cook
dd5052888d
refactor tilelink params, compiles but ExampleSmallConfig fails
2015-10-13 23:44:05 -07:00
Howard Mao
47da284e56
TileLinkNarrower should do nothing if interfaces are the same width
2015-10-13 13:28:47 -07:00
Howard Mao
a44e054c77
add support for different TileLink and MIF data widths
2015-10-13 12:46:23 -07:00
Howard Mao
83df05cb6a
add TileLink data narrower
2015-10-13 12:45:39 -07:00
Howard Mao
2fee3fd0fd
make sure NASTI -> SMI converter still works if words per beat is 1
2015-10-13 12:44:48 -07:00
Howard Mao
993ed86198
move ReorderQueue to utils.scala
2015-10-13 09:49:22 -07:00
Henry Cook
9d11b64c75
added HasAddrMapParameters and GlobalAddrMap
2015-10-06 18:24:08 -07:00
Henry Cook
4508666d96
log2ceil
2015-10-06 18:22:47 -07:00
Henry Cook
8173695800
added HasAddrMapParameters
2015-10-06 18:22:40 -07:00
Henry Cook
166df221ad
added HasAddrMapParameters
2015-10-06 18:15:16 -07:00
Henry Cook
1c489d75c1
inject params at top-level for MemDessert
2015-10-06 16:26:58 -07:00
Henry Cook
c4eadbda57
Removed all traces of params
2015-10-06 11:42:06 -07:00
Henry Cook
38ae2707a3
refactor MemIO to not use params
2015-10-06 11:41:48 -07:00
Henry Cook
3d10a89907
refactor NASTI to not use param; new AddrMap class
2015-10-06 11:41:47 -07:00
Henry Cook
84576650b5
Removed all traces of params
2015-10-05 21:48:05 -07:00
Henry Cook
adcd77db36
Removed all traces of params
2015-10-05 20:33:55 -07:00
Henry Cook
970445a26a
refactor MemIO to not use params
2015-10-02 15:37:41 -07:00
Henry Cook
69a4dd0a79
refactor NASTI to not use param
2015-10-02 14:20:47 -07:00
Henry Cook
39a749843c
refactor NASTI to not use param; new AddrMap class
2015-10-02 14:19:51 -07:00
Andrew Waterman
c2ad0b7dd4
Unfuck fpga-zynq submodule pointer
...
Sorry, Scott.
2015-10-01 15:00:35 -07:00
Andrew Waterman
996670a4a6
Point to correct Chisel commit
2015-10-01 10:31:29 -07:00
Howard Mao
a76f0bf8fb
fix involuntary release bug in rocket ProbeUnit
2015-09-30 17:26:48 -07:00
Howard Mao
19656e4abe
make sure to generate release from clean coh state on probe miss
2015-09-30 16:58:18 -07:00
Andrew Waterman
8da7be3211
More Chisel3 compatibility fixes
2015-09-30 14:37:40 -07:00
Andrew Waterman
0fe16ac1c0
Chisel3 compatibility fixes
2015-09-30 14:37:00 -07:00
Andrew Waterman
833909a2b5
Chisel3 compatibility fixes
2015-09-30 14:36:26 -07:00
Andrew Waterman
a7c908cb83
Don't declare Reg inside of when
...
We haven't yet decided what the Chisel3 semantics for this will be.
2015-09-30 12:43:36 -07:00
Howard Mao
2f3d15675c
fix DataArray writemask in L1D
2015-09-28 16:02:39 -07:00
Howard Mao
1e7f656527
get release block address from inner release
2015-09-28 15:02:51 -07:00
Andrew Waterman
79cdf6efc0
Make perf counters optional
2015-09-28 13:56:08 -07:00
Andrew Waterman
f8a7a80644
Make perf counters optional
2015-09-28 13:55:23 -07:00
Andrew Waterman
5e88ead984
Add pseudo-ops to instructions.scala
2015-09-28 11:52:27 -07:00
