riscv/rocket-chip
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806 Commits 1 Branch 0 Tags 13 MiB
1cb65d5ec1
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805 Commits

Author SHA1 Message Date
Henry Cook
1cb65d5ec1 %s/master/manager/g 2014-12-29 22:56:18 -08:00
Henry Cook
77e5e6b561 refill bug 2014-12-17 19:29:28 -08:00
Henry Cook
08dcf4c6ca refactor cache params 2014-12-17 14:28:05 -08:00
Henry Cook
d29793d1f7 cleanup CoherenceMetadata and coherence params 2014-12-15 19:23:38 -08:00
Henry Cook
c9320862ae add l2 dmem signal to rocc 2014-12-12 16:55:08 -08:00
Henry Cook
72ea24283b multibeat TL; passes all tests 2014-12-12 16:54:33 -08:00
Henry Cook
b7b2923bff Cleanup MSHR internal bundles 2014-11-11 18:18:35 -08:00
Henry Cook
c9e7874818 Major tilelink revision for uncached message types 2014-11-11 17:36:48 -08:00
Henry Cook
bf901e4bca Remove master_xact_id from Release 2014-11-06 12:09:45 -08:00
Andrew Waterman
7bb7299018 Don't pollute BTB with PC+4 target predictions 2014-10-14 17:28:37 -07:00
Andrew Waterman
cde7c9d869 simplify CSR decoding code 2014-10-03 14:31:26 -07:00
Christopher Celio
9cc35dee9a Returned history update to fetch. 
- Global history only contains branches.
   - Only update BHT and history on BTB hits.
   - Gate off speculative update on stall or icmiss.
   - Fixed bug where BHT updates were delayed a cycle.
 2014-09-29 21:41:07 -07:00
Christopher Celio
8ccd07cfeb Moved updating global history from fetch to decode. 
- No longer update global history in fetch stage.
   - Only update global history when instruction is a branch.
   - Does allow for the possibility of back-to-back branches to see
     slightly different histories on subsequent executions.
 2014-09-28 05:16:36 -07:00
Christopher Celio
681b43f398 Bug fixes with global history register. 
- Updated in fetch speculatively.
      * Updates gated off by cpu.resp.fire().
      * BTB direction factored into history update.
   - All branches update the BHT.
   - Each instruction carries history; index into BHT is recomputed by
     passing in mem_reg_pc.
 2014-09-26 10:39:57 -07:00
Christopher Celio
a71bdbbc54 Update history register in fetch speculatively 2014-09-26 05:42:08 -07:00
Christopher Celio
f917810061 Removed RocketCoreParameters from use. 
- The nbdache (among others?) use CoreParameters, which has nothing to do with RetireWidth requirements.
   - This conflicts with other cores which uses nbdcache.
   - RocketCoreParameters may be unneccessary, and the require() check can be moved deeper into Rocket.
 2014-09-26 05:14:50 -07:00
Christopher Celio
868e747656 Factored out Rocket specifics from CoreParameters 
- Added new RocketCoreParameters
   - Other cores using Rocket as a library will no longer conflict against
      Rocket's requires().
 2014-09-25 18:52:58 -07:00
Henry Cook
8eb64205f5 bug fix for nbdcache s2_data 2014-09-25 12:00:20 -07:00
Henry Cook
b55c38cdc7 Remove spurious vec consts 2014-09-25 12:00:20 -07:00
Adam Izraelevitz
3e256439c9 Add abstract class Tile 2014-09-24 13:04:20 -07:00
Yunsup Lee
238f7761f6 update README 2014-09-17 11:23:25 -07:00
Yunsup Lee
8abf62fae3 add LICENSE 2014-09-12 18:06:41 -07:00
Yunsup Lee
25180b71f7 add LICENSE 2014-09-12 15:36:42 -07:00
Andrew Waterman
a999c055ed Don't take an interrupt when EX stage PC is invalid 
It was possible to take an interrupt on the instruction in the shadow of
a short forward branch.  EPC would thus get the wrong value, and so
a wrong-path instruction would be executed upon return from interrupt.

h/t Yunsup
 2014-09-11 01:46:52 -07:00
Henry Cook
5eb5e9eaf5 Standardize ()=>Module(...) top-level Parameters 2014-09-07 17:54:41 -07:00
Henry Cook
5e2f98747f Merge branch 'dse' 2014-09-06 06:10:15 -07:00
Scott Beamer
600c5d50a9 better fix with explanation of sbt issue 2014-09-02 15:14:56 -07:00
Scott Beamer
f9922a106b fixes sbt error during first run 2014-09-02 14:34:36 -07:00
Henry Cook
b42a2ab40a Final parameter refactor 2014-09-01 13:28:58 -07:00
Adam Izraelevitz
2d6aafc32e Merge branch 'dse' of github.com:ucb-bar/rocket-staging into HEAD 2014-09-01 11:23:50 -07:00
Sagar Karandikar
83c6c2c9e2 rename refs to zynq-fpga to fpga-zynq 2014-08-29 10:26:48 -07:00
Henry Cook
6a4193cf90 minor cache param cleanup 2014-08-19 11:38:46 -07:00
Henry Cook
2de268b3b1 Cache utility traits. Completely compiles, asm tests hang. 2014-08-19 11:38:20 -07:00
Henry Cook
ca5f38ff26 a few more fixes. some param lookups fail (here() in Alter blocks) 2014-08-19 11:38:11 -07:00
Henry Cook
0dac9a7467 Full conversion to params. Compiles but does not elaborate. 2014-08-19 11:38:02 -07:00
Adam Izraelevitz
4e6d69892d Added initial brainstorm for parameter hierarchical flattening, does not compile ;) 2014-08-19 11:37:50 -07:00
Adam Izraelevitz
812353bace Ported FPU parameters to new Chisel Parameters 2014-08-19 11:37:27 -07:00
Yunsup Lee
4ac8e59b1f add .gitignore 2014-08-18 19:27:50 -07:00
Yunsup Lee
d520846638 add README and sbt files 2014-08-18 19:23:10 -07:00
Andrew Waterman
7bffc6c586 rename Unsigned.size to Unsigned.clog2 2014-06-14 13:58:07 -07:00
Andrew Waterman
3828c628c3 Remove vestigial control signals 2014-06-14 13:58:07 -07:00
Andrew Waterman
04593d433e clean up Int <-> Boolean conversion stuff 2014-06-14 13:58:07 -07:00
Andrew Waterman
ac88ded35a Use ROMs to reduce node count and improve QoR a bit 2014-06-14 13:58:07 -07:00
Andrew Waterman
88899eafe0 Reduce node count a bit 2014-06-14 13:58:07 -07:00
Jim Lawson
0c93567dea Replace needWidth() with getWidth. 2014-06-13 14:58:52 -07:00
Jim Lawson
de32595fba Quick change to work with new Width class. 2014-06-13 12:00:50 -07:00
Henry Cook
dab675b231 refactor Metadata, clean and expand coherence API 2014-05-28 16:05:48 -07:00
Andrew Waterman
8bc1c33540 Fix BTB error (requires Chisel update) 2014-05-19 18:56:30 -07:00
Andrew Waterman
cbb37ccc3e Use Mem instead of Vec[Reg] 2014-05-18 19:25:43 -07:00
Andrew Waterman
e91e12ed88 Fix RoCC accumulator example 2014-05-14 16:17:39 -07:00