riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
565 Commits 1 Branch 0 Tags 13 MiB
11bd15432a
Commit Graph

383 Commits

Author SHA1 Message Date
Andrew Waterman
27df04354f Add ROM with NASTI interface 2015-11-25 20:04:31 -08:00
Andrew Waterman
57e82442a1 Make LoadGen and StoreGen generic 2015-11-24 18:12:42 -08:00
Howard Mao
ee6514e4f4 make sure WritebackUnit sends correct probe addresses 2015-11-21 15:55:11 -08:00
Howard Mao
04383a31f5 Revert "make sure L2MetadataArray assigns unoccupied way if available" 
This reverts commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b.
 2015-11-21 10:35:40 -08:00
Howard Mao
3c95afebc6 Shift set index for multi-bank configurations 
Prior to this commit, the L2 cache banks used the lower bits of the
block address as the set index. However, the lower bits are also used to
route addresses to different banks. As a result, in multi-bank
configurations, only a fraction of the sets in each bank could be
accessed. This commit fixes that problem by using the bits ahead of the
bank index as the set index, so that all sets in the cache can be
accessed.
 2015-11-20 23:24:57 -08:00
Howard Mao
55a85cc67a make sure wmask is passed for PutBlock in broadcast hub 2015-11-20 14:09:24 -08:00
Howard Mao
941b64cd62 make partial write-masking PutBlock constructor always set alloc bit 2015-11-20 13:34:07 -08:00
Howard Mao
24f7b9f472 make sure L2MetadataArray assigns unoccupied way if available 2015-11-19 10:45:54 -08:00
Howard Mao
e50c7ad306 add NASTI error assertions back in 2015-11-18 17:05:54 -08:00
Henry Cook
2b977325e3 Make prefetch type available in a_type, issue probeInvalidates for putPrefetches 2015-11-16 23:26:13 -08:00
Andrew Waterman
d426ecee78 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:52:24 -08:00
Henry Cook
0290635454 amo_shift_bits -> amo_shift_bytes 2015-11-16 19:07:58 -08:00
Henry Cook
64aaf71b06 L2AcquireTracker refactor to support merging Gets and Puts into Prefetches of the correct type. 
Transaction metadata for primary and seconday misses now stored in the secondary miss queue.

Added BuiltInAcquireBuilder factory.
 2015-11-16 18:10:09 -08:00
Henry Cook
03fa06e6e7 fix prefetch lockup on L2 hit 2015-11-15 12:51:34 -08:00
Howard Mao
e12efab423 skip meta_write state if no meta write pending 2015-11-13 13:50:35 -08:00
Howard Mao
7e7d688a01 make sure L2 passes no-alloc acquires through to outer memory 2015-11-12 15:40:58 -08:00
Howard Mao
b3865c370a make sure correct addr_beat is sent for Get response by narrower/converter 2015-11-12 15:40:38 -08:00
Howard Mao
f397d61033 add alloc option to Put constructor 2015-11-12 11:39:59 -08:00
Howard Mao
7733fbe6a3 make sure no-alloc write still updates data array if there is a cache hit 2015-11-12 11:39:36 -08:00
Howard Mao
b59ce5fed4 make sure L2 waits for outer grant before sending grant for write request 2015-11-10 16:06:14 -08:00
Howard Mao
42d3d09d7a add a ClientTileLinkEnqueuer to complement the TileLinkEnqueuer 2015-11-09 11:49:19 -08:00
Howard Mao
7942be4e01 make sure outerTL method is idempotent 2015-11-09 11:10:02 -08:00
Henry Cook
e3efc09b5b remove unnecessary UInt encode/decode on releaseMatches path 2015-11-05 17:20:03 -08:00
Henry Cook
3698153535 OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank 2015-11-03 14:31:35 -08:00
Howard Mao
baa2544651 Fix some more issues with narrower 2015-10-31 19:36:30 -07:00
Howard Mao
812c5bcc55 make sure narrower can handle sub-block level requests correctly 2015-10-31 15:58:36 -07:00
Howard Mao
d4b8653002 fix too strict assertion in broadcast hub 2015-10-31 15:58:10 -07:00
Howard Mao
c10870a87c make sure ID width requirement in TL -> NASTI converter is correct 2015-10-27 13:25:29 -07:00
Howard Mao
9fa4541916 get rid of unused full signal in ReorderQueue 2015-10-26 12:17:25 -07:00
Howard Mao
6403f27fbe fix bug in ReorderQueue breaking TileLink Unwrapper 2015-10-22 15:52:55 -07:00
Henry Cook
f8594da1d3 depend on external cde library 2015-10-21 18:17:17 -07:00
Howard Mao
02d113b39f outerDataBits / innerDataBits should be per beat, not per block 2015-10-21 11:31:13 -07:00
Howard Mao
baf95533a4 fix combinational loop in TileLink Unwrapper 2015-10-20 23:26:11 -07:00
Howard Mao
ffe7df2fed make sure TL -> NASTI converter acquire ready not dependent on valid 2015-10-20 22:09:22 -07:00
Howard Mao
1c135c1628 fix ready-valid mixup in TileLink unwrapper 2015-10-20 21:07:42 -07:00
Henry Cook
4389b9edb0 tilelink parameter tweak: addrBits now a constant 2015-10-20 15:00:30 -07:00
Howard Mao
d12403e7dc fix up and simplify TL -> NASTI converter logic 2015-10-19 13:47:13 -07:00
Henry Cook
d391f97953 Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU. 2015-10-16 19:11:06 -07:00
Henry Cook
e1f573918d simplify TileLinkParameters with Option 2015-10-16 18:24:38 -07:00
Howard Mao
49667aa4b0 make sure broadcast acquire tracker doesn't try to send requests back-to-back 2015-10-14 18:56:13 -07:00
Howard Mao
1d362d6d3a make sure correct parameters are used for TileLink constructors 2015-10-14 17:58:54 -07:00
Henry Cook
7fa3eb95e3 refactor tilelink params 2015-10-14 12:13:37 -07:00
Henry Cook
66ea39638e GlobalAddrMap 2015-10-14 00:23:28 -07:00
Henry Cook
31be6407ec Removed all traces of params 2015-10-14 00:23:28 -07:00
Henry Cook
908922c1a4 refactor NASTI to not use param 2015-10-14 00:23:28 -07:00
Howard Mao
47da284e56 TileLinkNarrower should do nothing if interfaces are the same width 2015-10-13 13:28:47 -07:00
Howard Mao
83df05cb6a add TileLink data narrower 2015-10-13 12:45:39 -07:00
Howard Mao
993ed86198 move ReorderQueue to utils.scala 2015-10-13 09:49:22 -07:00
Andrew Waterman
0fe16ac1c0 Chisel3 compatibility fixes 2015-09-30 14:37:00 -07:00
Howard Mao
1e7f656527 get release block address from inner release 2015-09-28 15:02:51 -07:00
Andrew Waterman
3b1da4c57e Revert "replace remaining uses of Vec.fill" 
This reverts commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47.
 2015-09-25 17:06:57 -07:00
Andrew Waterman
20b7a82ab6 Use Vec.fill, not Vec.apply, when making Vec literals 2015-09-25 17:06:52 -07:00
Andrew Waterman
2179cb64ae Let isRead be true for store-conditional 
This works around a deadlock bug in the L1 D$, and is arguably true.
 2015-09-25 15:28:02 -07:00
Howard Mao
308022210a use updated NASTI channel constructors 2015-09-25 12:07:27 -07:00
Howard Mao
8c4ac0f4f3 make sure CSR/SCR data width matches xLen 2015-09-25 12:07:03 -07:00
Howard Mao
d1f2d40a90 replace remaining uses of Vec.fill 2015-09-24 17:50:09 -07:00
Howard Mao
3ff830e118 ReorderQueue uses Vec of Bools instead of Bits for roq_free 2015-09-24 17:43:53 -07:00
Howard Mao
83740dfaa5 Merge branch 'master' of github.com:ucb-bar/uncore 2015-09-24 17:10:09 -07:00
Howard Mao
3b86790c3f replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:58:20 -07:00
ducky
ee6754daca Fix clone -> cloneType 2015-09-24 16:18:25 -07:00
Howard Mao
b4d21148ec get rid of NASTI error assertion 2015-09-22 09:43:42 -07:00
Howard Mao
8b2341b1b1 use reorder queue instead of extra tag bit to determine TL g_type in NASTI -> TL converter 2015-09-18 09:41:37 -07:00
Howard Mao
bd536d8832 make HTIFModuleIO an anonymous bundle 2015-09-14 12:58:44 -07:00
Howard Mao
9d89d2a558 get rid of MemIO -> TileLink converters 2015-09-14 12:58:44 -07:00
Howard Mao
f9965648f2 fix up some things in tilelink.scala 2015-09-14 12:57:54 -07:00
Howard Mao
64717706a9 get rid of non-NASTI RTC module 2015-09-14 12:57:54 -07:00
Howard Mao
6ee6ea4f1e use Put/Get/PutBlock/GetBlock constructors in broadcast hub 2015-09-14 12:57:54 -07:00
Howard Mao
ae3d96013a make TL -> NASTI converter ingest ClientUncachedTileLinkIO and move functionality to Unwrapper 2015-09-14 12:57:54 -07:00
Howard Mao
21f96f382c split off SCR functionality from HTIF 2015-09-14 12:57:54 -07:00
Howard Mao
bdc6972a8d separate RTC updates from HTIF 2015-09-14 12:56:44 -07:00
Howard Mao
24f3fac90a fix broadcast hub and TL -> NASTI converter to support subblock operations 2015-09-14 12:56:44 -07:00
Andrew Waterman
24389a5257 Chisel3 compatibility fixes 2015-09-11 15:41:39 -07:00
Andrew Waterman
350d530766 Use Vec.fill, not Vec.apply, for Vec literals 2015-08-27 10:00:43 -07:00
Andrew Waterman
94287fed90 Avoid type-unsafe assignments 2015-08-27 09:57:36 -07:00
Andrew Waterman
05d311c517 Use Vec.apply, not Vec.fill, for type nodes 2015-08-27 09:47:02 -07:00
Henry Cook
005752e2a6 use the parameters used to create the original object 2015-08-10 14:43:17 -07:00
Andrew Waterman
01fc61ba96 Don't construct so many Vecs 2015-08-05 18:43:59 -07:00
Howard Mao
a551a12d70 add missing Wire wrap in BasicCrossbar 2015-08-05 17:05:31 -07:00
Andrew Waterman
eb6583d607 use cloneType in PhysicalNetworkIO 2015-08-05 16:47:49 -07:00
Andrew Waterman
798ddeb5f5 Chisel3 compatibility: use >>Int instead of >>UInt 
The latter doesn't contract widths anymore.
 2015-08-04 13:15:17 -07:00
Andrew Waterman
77cf26aeba Chisel3: Flip order of := and <> 2015-08-03 18:53:39 -07:00
Andrew Waterman
121e4fb511 Flip direction of some bulk connects 2015-08-03 18:01:14 -07:00
Andrew Waterman
a21979a2fa Bits -> UInt 2015-08-03 18:01:06 -07:00
Andrew Waterman
9c7a41e8d3 Chisel3: bulk connect is not commutative 
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with.  Should make
for lively debate.
 2015-08-01 21:09:00 -07:00
Andrew Waterman
6fc807f069 Chisel3: Avoid subword assignment 2015-08-01 21:08:35 -07:00
Andrew Waterman
6d574f8c1b Fix incompatible assignment 2015-07-31 00:59:34 -07:00
Andrew Waterman
377e17e811 Add Wire() wrap 2015-07-31 00:32:02 -07:00
Andrew Waterman
0686bdbe28 Avoid cross-module references 
You can't instantiate a Vec in one module and use it in another.
An idiosyncrasy of the Chisel2 implementation let this one slip by.
In this case, it's just a matter of using def instead of val.
 2015-07-30 23:49:06 -07:00
Andrew Waterman
8f7b390353 UInt-> Bits; avoid mixed UInt/SInt code 2015-07-30 23:49:06 -07:00
Andrew Waterman
6c391e3b37 Use UInt(0), not UInt(width=0), for constant 0 2015-07-30 23:49:06 -07:00
Henry Cook
c70b495f6d moved buses to junctions repo 2015-07-29 18:04:30 -07:00
Andrew Waterman
a69c749249 Fix compilation with scala 2.11.6 
We forgot to specify return types on overloaded methods, and a previous
version of the scala compiler failed to flag this as an error.
 2015-07-28 16:24:45 -07:00
Andrew Waterman
f8ec6d6393 Chisel3 compatibility: use BitPat for don't-cares 
Also, call the UInt factory instead of the Bits one, for good measure.
 2015-07-28 02:46:23 -07:00
Andrew Waterman
0e06c941df Chisel3 compatibility fixes 2015-07-23 14:58:46 -07:00
Andrew Waterman
3c0475e08b Add Wire() wrap 2015-07-15 20:24:03 -07:00
Andrew Waterman
2d6b3b2331 Don't use clone 2015-07-15 18:06:27 -07:00
Andrew Waterman
276f53b652 Delete BigMem; it's not used anymore 2015-07-15 17:41:47 -07:00
Andrew Waterman
15cec0eab7 Vec(Reg) -> Reg(Vec) 2015-07-15 12:44:54 -07:00
Andrew Waterman
e76a9d3493 Chisel3: Don't mix Mux types 2015-07-11 14:05:39 -07:00
Andrew Waterman
5dc3da008e Use Chisel3 SeqMem construct 2015-07-11 13:36:26 -07:00