Henry Cook
|
faed47d131
|
use thunk for dir info
|
2014-09-20 16:54:28 -07:00 |
|
Henry Cook
|
f7b1e23ead
|
functional style on MuxBundle
|
2014-09-20 16:54:28 -07:00 |
|
Yunsup Lee
|
f249da1803
|
update README
|
2014-09-17 11:25:14 -07:00 |
|
Yunsup Lee
|
49b027db2c
|
forgot to add LICENSE file
|
2014-09-12 15:36:29 -07:00 |
|
Yunsup Lee
|
0b51d70bd2
|
add LICENSE
|
2014-09-12 15:31:38 -07:00 |
|
Yunsup Lee
|
f8d450b4e2
|
mark DRAMSideLLC as HasKnownBug
|
2014-09-11 22:06:03 -07:00 |
|
Henry Cook
|
5e26b4ab66
|
Merge branch 'dse'
Conflicts:
src/main/scala/htif.scala
src/main/scala/llc.scala
|
2014-09-06 06:16:58 -07:00 |
|
Scott Beamer
|
f8821b4cc9
|
better fix with explanation of sbt issue
|
2014-09-02 15:16:03 -07:00 |
|
Scott Beamer
|
bfb662968d
|
fixes sbt error during first run
|
2014-09-02 14:33:58 -07:00 |
|
Henry Cook
|
712f3a754d
|
merge in master
|
2014-09-02 12:34:42 -07:00 |
|
Henry Cook
|
17b2359c9a
|
htif parameters trait
|
2014-08-24 19:27:58 -07:00 |
|
Henry Cook
|
dc5643b12f
|
Final parameter refactor.
|
2014-08-23 01:19:36 -07:00 |
|
Scott Beamer
|
e384b33cc3
|
don't generate a write mask for BigMem if it isn't used
not needed for llc data
|
2014-08-19 15:50:20 -07:00 |
|
Henry Cook
|
e26f8a6f6a
|
Fix errors in derived cache params
|
2014-08-12 14:55:44 -07:00 |
|
Henry Cook
|
9ab3a4262c
|
Cache utility traits. Completely compiles, asm tests hang.
|
2014-08-11 18:35:49 -07:00 |
|
Henry Cook
|
f411fdcce3
|
Full conversion to params. Compiles but does not elaborate.
|
2014-08-08 12:21:57 -07:00 |
|
Jim Lawson
|
0020ded367
|
Replace needWidth() with getWidth.
|
2014-06-13 14:53:48 -07:00 |
|
Jim Lawson
|
a04ef4f5f4
|
Quick change to work with new Width class.
Replace .width with .needWidth()
|
2014-06-13 11:44:43 -07:00 |
|
Andrew Waterman
|
1ae7a9376c
|
Fix unhandled LLC writeback hazard
|
2014-06-13 03:25:52 -07:00 |
|
Henry Cook
|
3c329df7e7
|
refactor Metadata, clean and expand coherence API
|
2014-05-28 13:35:08 -07:00 |
|
Andrew Waterman
|
364a6de214
|
Use Mem instead of Vec[Reg]
|
2014-05-18 19:26:35 -07:00 |
|
Henry Cook
|
0e39346a12
|
L2-specific metadataarray wrapper, hookups to tshrfile
|
2014-05-07 01:51:46 -07:00 |
|
Henry Cook
|
bc3ef1011e
|
correct use of function value to initialize MetaDataArray
|
2014-05-06 12:59:45 -07:00 |
|
Henry Cook
|
45172f1f37
|
parameterize metadataarray
|
2014-05-01 01:44:59 -07:00 |
|
Henry Cook
|
0237229921
|
client/master -> inner/outer
|
2014-04-29 16:49:18 -07:00 |
|
Henry Cook
|
52c6de5641
|
DRAMSideLLCLike trait. TSHRFile. New L2 config objects.
|
2014-04-26 19:11:36 -07:00 |
|
Henry Cook
|
1163131d1e
|
TileLinkIO.GrantAck -> TileLinkIO.Finish
|
2014-04-26 15:17:05 -07:00 |
|
Henry Cook
|
3f53d532c2
|
uniquify tilelink conf val name for easier subtyping
|
2014-04-26 14:58:38 -07:00 |
|
Henry Cook
|
f8f29c69b8
|
MetaData & friends moved to uncore/
|
2014-04-23 16:24:20 -07:00 |
|
Henry Cook
|
39681303b8
|
beginning of l2 cache
|
2014-04-22 16:58:15 -07:00 |
|
Henry Cook
|
5613dc7d1b
|
replaced Lists with Vecs
|
2014-04-18 17:26:56 -07:00 |
|
Jim Lawson
|
bf2ff7804e
|
Add chisel-dependent.sbt for -DchiselVersion="latest.release"
If -DchiselVersion is specified on the command line, add the
appropriate chisel library to libraryDependencies.
|
2014-04-17 17:01:40 -07:00 |
|
Henry Cook
|
b1df49ba30
|
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
|
2014-04-10 12:35:43 -07:00 |
|
Henry Cook
|
fbca7c6bb3
|
refactor ioMem and associcated constants. merge Aqcuire and AcquireData
|
2014-04-10 12:35:43 -07:00 |
|
Jim Lawson
|
a228dbfa0d
|
Revert "Update library dependencies (jenkins builds)"
This reverts commit e7a12143d0bfe8b3b4a4dcc78d119a89553ade8c.
|
2014-03-20 10:40:05 -07:00 |
|
Jim Lawson
|
dec98eb047
|
Update library dependencies (jenkins builds)
Add chisel as an explicit library dependency
|
2014-03-18 11:37:08 -07:00 |
|
Andrew Waterman
|
02dbd6b0aa
|
Don't assign to your own inputs
|
2014-02-12 18:39:40 -08:00 |
|
Henry Cook
|
bbf8010230
|
cleanups supporting uncore hierarchy
|
2014-01-31 15:59:21 -08:00 |
|
Andrew Waterman
|
3e634aef1d
|
Fix HTIF for cache line sizes other than 64 B
|
2014-01-22 18:20:36 -08:00 |
|
Andrew Waterman
|
4f1213cb8b
|
Fix Scala integer overflow
|
2014-01-13 21:45:14 -08:00 |
|
Andrew Waterman
|
acc0d2b06c
|
Only use LSBs for HTIF control regs
For now, at least...
|
2013-11-25 04:34:16 -08:00 |
|
Yunsup Lee
|
056bb156ca
|
make CacheConstants an object
|
2013-11-20 16:43:55 -08:00 |
|
Yunsup Lee
|
f13d76628b
|
forgot to put htif into uncore package
|
2013-11-07 15:42:10 -08:00 |
|
Yunsup Lee
|
c350cbd6ea
|
move htif to uncore
|
2013-11-07 13:19:04 -08:00 |
|
Yunsup Lee
|
f440df5338
|
rename M_FENCE to M_NOP
|
2013-10-28 22:37:41 -07:00 |
|
Henry Cook
|
42693d43ad
|
simplify build.sbt
|
2013-09-26 09:51:14 -07:00 |
|
Stephen Twigg
|
20246b373e
|
Properly ignore target files
|
2013-09-24 16:02:00 -07:00 |
|
Huy Vo
|
cc3dc1bd0f
|
bug fix
|
2013-09-19 20:10:56 -07:00 |
|
Andrew Waterman
|
cc7783404d
|
Add memory command M_XA_XOR
|
2013-09-12 16:09:53 -07:00 |
|
Henry Cook
|
1cac26fd76
|
NetworkIOs no longer use thunks
|
2013-09-10 16:15:41 -07:00 |
|
Henry Cook
|
ee98cd8378
|
new enum syntax
|
2013-09-10 10:54:51 -07:00 |
|
Stephen Twigg
|
e23e8e3850
|
Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/memserdes.scala
|
2013-09-05 16:17:34 -07:00 |
|
Yunsup Lee
|
b01fe4f6aa
|
fix memserdes bit ordering
|
2013-08-24 15:24:17 -07:00 |
|
Henry Cook
|
9aff60f340
|
whitespace error in build.sbt
|
2013-08-21 16:16:42 -07:00 |
|
Henry Cook
|
dc53529156
|
added resolver, bumped chisel dependency
|
2013-08-21 16:00:51 -07:00 |
|
Henry Cook
|
b80f45f8f2
|
Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2
Conflicts:
src/main/scala/llc.scala
src/main/scala/slowio.scala
|
2013-08-15 16:22:12 -07:00 |
|
Henry Cook
|
3763cd0004
|
standardizing sbt build conventions
|
2013-08-15 15:57:16 -07:00 |
|
Henry Cook
|
17d404b325
|
final Reg changes
|
2013-08-15 15:27:38 -07:00 |
|
Henry Cook
|
1308c08baa
|
Reg standardization
|
2013-08-13 17:52:53 -07:00 |
|
Henry Cook
|
7ff4126d04
|
Abstracted UncachedTileLinkIOArbiters
|
2013-08-13 00:01:11 -07:00 |
|
Henry Cook
|
9162fbc9b5
|
Clean up cloning in tilelink bundles
|
2013-08-12 23:15:54 -07:00 |
|
Huy Vo
|
d5c9eb0f54
|
reset -> resetVal, getReset -> reset
|
2013-08-12 20:52:18 -07:00 |
|
Henry Cook
|
5c7a1f5cd6
|
initial attempt at upgrade
|
2013-08-12 10:36:44 -07:00 |
|
Henry Cook
|
bc2b45da12
|
Fold uncore constants into TileLinkConfiguration, update coherence API
|
2013-08-02 14:55:06 -07:00 |
|
Henry Cook
|
d8440b042a
|
Make compatible with scala 2.10. Refactor constants into package object. Remove networking primitives from package object. Clean up request generators. Chnage ++ to +: for appending to io.incoherent.
|
2013-07-24 23:22:36 -07:00 |
|
Henry Cook
|
db8e5fda9b
|
new tilelink arbiter types, reduced release xact trackers
|
2013-07-09 15:37:42 -07:00 |
|
Henry Cook
|
9631b6081e
|
Merge branch 'tilelink-data'
Conflicts:
src/package.scala
|
2013-05-23 14:53:10 -07:00 |
|
Henry Cook
|
cf02f1ef01
|
use new locking round robin arbiter
|
2013-05-23 14:16:50 -07:00 |
|
Henry Cook
|
4c1f105ce9
|
added PairedData link type with matching crossbar, ported tilelink and uncore to use
|
2013-05-21 17:19:07 -07:00 |
|
Andrew Waterman
|
0672773c1a
|
for now, don't use asserts outside of components
|
2013-05-09 02:14:44 -07:00 |
|
Henry Cook
|
9a3b2e7006
|
new paired meta/data IO type, and matching arbiter
|
2013-05-01 17:18:12 -07:00 |
|
Henry Cook
|
9a258e7fb4
|
use new locking round robin arbiter
|
2013-04-30 17:10:06 -07:00 |
|
Henry Cook
|
fedc2753e4
|
make sure master_xact_id field is large enough for temporary extra release trackers
|
2013-04-30 11:03:34 -07:00 |
|
Henry Cook
|
12d394811e
|
Allow release data to be written out even before all releases have been collected
|
2013-04-29 18:48:31 -07:00 |
|
Henry Cook
|
766d5622b1
|
Prevent messages from becoming interleaved in the BasicCrossbar. Remove dependency trackers from the uncore, use msg headers instead. Have one ReleaseHnadler per core for now.
|
2013-04-10 13:46:31 -07:00 |
|
Henry Cook
|
74187c2068
|
Always route voluntary releases to ReleaseTracker to ensure all grants are sent
|
2013-04-09 14:09:55 -07:00 |
|
Andrew Waterman
|
7ff5b5b86f
|
treat load-reserved as a non-dirtying store
|
2013-04-07 19:25:26 -07:00 |
|
Andrew Waterman
|
3479f1c6cd
|
add LR/SC support
|
2013-04-07 19:25:20 -07:00 |
|
Henry Cook
|
b6cc08e8ca
|
override io in LogicalNetwork
|
2013-03-28 14:09:48 -07:00 |
|
Henry Cook
|
67fc09f62e
|
Fixes after merge, and always self probe.
|
2013-03-25 19:12:19 -07:00 |
|
Henry Cook
|
06f5de3b68
|
Merge branch 'release-xacts'
Conflicts:
src/package.scala
src/uncore.scala
|
2013-03-20 17:38:46 -07:00 |
|
Henry Cook
|
4d007d5c40
|
changed val names in hub to match new tilelink names
|
2013-03-20 17:14:07 -07:00 |
|
Henry Cook
|
c36b1dfa30
|
Cleaned up uncore and coherence interface. Removed defunct broadcast hub. Trait-ified tilelink bundle components. Added generalized mem arbiter.
|
2013-03-20 15:52:39 -07:00 |
|
Henry Cook
|
319b4544d7
|
nTiles -> nClients in LogicalNetworkConfig
|
2013-03-20 14:30:16 -07:00 |
|
Henry Cook
|
a7ae7e5758
|
Cleaned up self-probes
|
2013-03-20 14:28:20 -07:00 |
|
Andrew Waterman
|
7b019cb0da
|
rmeove aborts
|
2013-03-19 15:30:23 -07:00 |
|
Yunsup Lee
|
f120800aa2
|
add DRAMSideLLCNull
|
2013-03-19 00:41:28 -07:00 |
|
Yunsup Lee
|
717a78f964
|
fix seqRead inference
|
2013-03-19 00:41:09 -07:00 |
|
Henry Cook
|
9f0ccbeac5
|
writebacks on release network pass asm tests and bmarks
|
2013-02-28 18:13:41 -08:00 |
|
Andrew Waterman
|
944f56a766
|
remove duplicate definitions
|
2013-02-28 14:55:19 -08:00 |
|
Henry Cook
|
47a632cc59
|
added support for voluntary wbs over the release network
|
2013-01-28 16:39:45 -08:00 |
|
Henry Cook
|
1134bbf1a4
|
cleanup disconnected io pins (overwritten network headers)
|
2013-01-27 11:59:17 -08:00 |
|
Andrew Waterman
|
1945fa898b
|
make external clock divider programmable
|
2013-01-24 23:40:47 -08:00 |
|
Henry Cook
|
b5ccdab514
|
changed val names in hub to match new tilelink names
|
2013-01-22 20:09:21 -08:00 |
|
Henry Cook
|
c211d74e95
|
New TileLink names
|
2013-01-21 17:17:26 -08:00 |
|
Henry Cook
|
fb2644760f
|
single-ported coherence master
|
2013-01-16 23:57:35 -08:00 |
|
Henry Cook
|
f7c0152409
|
Refactored packet headers/payloads
|
2013-01-15 15:52:47 -08:00 |
|
Henry Cook
|
418e3fdf50
|
Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink
|
2013-01-07 13:57:48 -08:00 |
|
Henry Cook
|
400d48e3de
|
Refactored uncore conf
|
2012-12-13 11:39:14 -08:00 |
|
Henry Cook
|
6d61baa6cd
|
Initial version of phys/log network compiles
|
2012-12-12 11:08:50 -08:00 |
|
Henry Cook
|
f359518e52
|
wip: new network classes
|
2012-12-12 11:08:50 -08:00 |
|
Andrew Waterman
|
aae7a67781
|
fix llc refill/writeback bugs
|
2012-12-06 02:07:03 -08:00 |
|
Andrew Waterman
|
50e9d952e8
|
don't initiate llc refill until writeback drains
|
2012-12-04 06:57:53 -08:00 |
|
Andrew Waterman
|
8103676b37
|
reduce physical address space to 4GB
|
2012-11-26 20:54:56 -08:00 |
|
Andrew Waterman
|
56f9b9721d
|
treat prefetches as read requests
|
2012-11-20 05:38:49 -08:00 |
|
Yunsup Lee
|
6bd4f93f8c
|
pull out prefetch commands from isRead
|
2012-11-18 03:13:17 -08:00 |
|
Andrew Waterman
|
3e6dc35809
|
issue self-probes for uncached read transactions
this facilitates I$ coherence. but it seems like a hack and perhaps
the mechanism should be rethought.
|
2012-11-16 02:37:56 -08:00 |
|
Henry Cook
|
0cd0f8a9db
|
Initial version of migratory protocol
|
2012-10-23 18:01:53 -07:00 |
|
Andrew Waterman
|
2aecb0024f
|
UncoreConfiguration now contains coherence policy
|
2012-10-18 16:57:28 -07:00 |
|
Andrew Waterman
|
ffda0e41a9
|
parameterize width of MemSerdes/MemDesser
|
2012-10-18 16:56:36 -07:00 |
|
Henry Cook
|
9df5cfa552
|
Factored out tilelink classes
|
2012-10-16 14:26:33 -07:00 |
|
Henry Cook
|
8509cda813
|
Refined traits for use with rocket asserts, added UncoreConfiguration to handle ntiles
|
2012-10-16 13:58:18 -07:00 |
|
Henry Cook
|
1418604bf0
|
new constants organization
|
2012-10-15 18:52:48 -07:00 |
|
Huy Vo
|
08ab076217
|
forgot to change package + using fromBits in memserdes instead of manual unpacking
|
2012-10-10 15:42:39 -07:00 |
|
Huy Vo
|
9610622ab0
|
moving memserdes + slowio into src
|
2012-10-10 12:41:11 -07:00 |
|
Huy Vo
|
35f213e735
|
Merge branch 'master' of ../rocket-clone
|
2012-10-10 12:39:48 -07:00 |
|
Andrew Waterman
|
3973aef938
|
handle structural hazard on LLC tags
|
2012-10-09 18:04:55 -07:00 |
|
Huy Vo
|
916c1019af
|
fixed memdessert unpacking
|
2012-10-09 13:03:17 -07:00 |
|
Huy Vo
|
cf8f20584e
|
factoring out uncore into separate uncore repo
|
2012-10-01 16:08:41 -07:00 |
|
Huy Vo
|
2413763f3d
|
henry's uncore and rocket changes for new xact types
|
2012-10-01 16:05:37 -07:00 |
|
Henry Cook
|
da6ec486f1
|
uncore and rocket changes for new xact types
|
2012-10-01 10:47:36 -07:00 |
|
Huy Vo
|
fa8075570a
|
move srcs into src dir, factoring out uncore consts into consts
|
2012-09-27 12:59:45 -07:00 |
|
Andrew Waterman
|
6546dc84e2
|
rename queue to Queue
fixes build with case-insensitive file system
|
2012-08-08 22:11:59 -07:00 |
|
Andrew Waterman
|
aa7fd1f40b
|
rename queue to Queue
fixes build with case-insensitive file system
|
2012-08-08 22:11:59 -07:00 |
|
Andrew Waterman
|
17dc2075dd
|
fix some LLC control bugs
|
2012-08-06 17:10:04 -07:00 |
|
Andrew Waterman
|
115c25c34b
|
fix some LLC control bugs
|
2012-08-06 17:10:04 -07:00 |
|
Andrew Waterman
|
875f3622af
|
fix deadlock in coherence hub
|
2012-08-03 19:00:03 -07:00 |
|
Andrew Waterman
|
962423d2d1
|
fix deadlock in coherence hub
|
2012-08-03 19:00:03 -07:00 |
|
Andrew Waterman
|
e346f21725
|
fix control bug in LLC
structural hazard on tag ram caused deadlock
|
2012-08-03 18:59:37 -07:00 |
|
Andrew Waterman
|
92b7504c9a
|
fix control bug in LLC
structural hazard on tag ram caused deadlock
|
2012-08-03 18:59:37 -07:00 |
|
Andrew Waterman
|
7a75334bb9
|
pipeline LLC further
|
2012-07-31 17:45:14 -07:00 |
|
Andrew Waterman
|
7b9cfd0b90
|
pipeline LLC further
|
2012-07-31 17:45:14 -07:00 |
|
Andrew Waterman
|
8db233c9b7
|
further pipeline the LLC
|
2012-07-30 20:12:11 -07:00 |
|
Andrew Waterman
|
85dc34df80
|
further pipeline the LLC
|
2012-07-30 20:12:11 -07:00 |
|
Yunsup Lee
|
4d4e28c138
|
remove reset pin on llc
|
2012-07-28 21:14:51 -07:00 |
|
Yunsup Lee
|
914b6b622d
|
remove reset pin on llc
|
2012-07-28 21:14:51 -07:00 |
|
Yunsup Lee
|
465f2efca7
|
add reset pin to llc
|
2012-07-27 18:44:39 -07:00 |
|
Yunsup Lee
|
0a2d284d24
|
add reset pin to llc
|
2012-07-27 18:44:39 -07:00 |
|
Andrew Waterman
|
1ae3091261
|
memory system bug fixes
|
2012-07-26 00:05:21 -07:00 |
|
Andrew Waterman
|
1405718ca8
|
memory system bug fixes
|
2012-07-26 00:05:21 -07:00 |
|
Yunsup Lee
|
7736405726
|
fix bug in coherence hub, respect xact_rep.ready
|
2012-07-23 20:56:55 -07:00 |
|
Yunsup Lee
|
d0e12c13f6
|
fix bug in coherence hub, respect xact_rep.ready
|
2012-07-23 20:56:55 -07:00 |
|
Andrew Waterman
|
df8aff0906
|
don't dequeue probe queue during reset
|
2012-07-22 21:05:52 -07:00 |
|
Andrew Waterman
|
c6ac836581
|
don't dequeue probe queue during reset
|
2012-07-22 21:05:52 -07:00 |
|
Andrew Waterman
|
d01e70c672
|
decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
|
2012-07-17 22:55:40 -07:00 |
|
Andrew Waterman
|
0258dfb23f
|
decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
|
2012-07-17 22:55:40 -07:00 |
|
Huy Vo
|
a79747a062
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
Huy Vo
|
18bc14058b
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
Andrew Waterman
|
62a3ea4113
|
fix some LLC bugs
|
2012-07-11 17:56:39 -07:00 |
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Andrew Waterman
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0aa33bf909
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fix some LLC bugs
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2012-07-11 17:56:39 -07:00 |
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