2014-09-12 19:15:04 +02:00
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// See LICENSE for license details.
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2014-09-02 22:51:57 +02:00
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package rocketchip
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2014-08-23 10:26:03 +02:00
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import Chisel._
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2015-07-30 02:56:19 +02:00
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import junctions._
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2016-08-11 02:20:00 +02:00
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import rocket._
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2016-09-03 00:59:16 +02:00
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import rocket.Util._
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2016-06-28 22:16:48 +02:00
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import uncore.agents._
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2016-08-11 02:20:00 +02:00
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import uncore.tilelink._
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2016-06-28 22:16:48 +02:00
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import uncore.devices._
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2016-07-07 01:54:58 +02:00
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import uncore.converters._
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2016-08-11 02:20:00 +02:00
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import coreplex._
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2015-06-26 08:17:35 +02:00
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import scala.math.max
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2016-08-02 04:07:03 +02:00
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import scala.collection.mutable.{LinkedHashSet, ListBuffer}
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2016-08-20 03:26:34 +02:00
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import scala.collection.immutable.HashMap
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2015-07-13 23:54:26 +02:00
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import DefaultTestSuites._
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2016-04-22 04:37:08 +02:00
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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2014-08-23 10:26:03 +02:00
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2016-08-11 02:20:00 +02:00
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class BasePlatformConfig extends Config (
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2014-10-06 22:43:40 +02:00
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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2016-04-29 01:15:31 +02:00
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lazy val internalIOAddrMap: AddrMap = {
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2016-05-03 03:08:33 +02:00
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val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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2016-06-04 02:29:05 +02:00
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entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
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entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
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2016-06-06 13:51:55 +02:00
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entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
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2016-09-03 00:59:16 +02:00
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if (site(DataScratchpadSize) > 0) { // TODO heterogeneous tiles
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require(site(NTiles) == 1) // TODO relax this
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require(site(NMemoryChannels) == 0) // TODO allow both scratchpad & DRAM
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entries += AddrMapEntry("dmem0", MemRange(0x80000000L, site[Int](DataScratchpadSize), MemAttr(AddrMapProt.RWX)))
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}
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2016-05-03 03:08:33 +02:00
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new AddrMap(entries)
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2015-11-26 06:10:09 +01:00
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}
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2016-08-10 07:19:08 +02:00
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lazy val externalAddrMap = new AddrMap(
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2016-09-07 09:05:00 +02:00
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site(ExtraDevices).addrMapEntries ++ site(ExtMMIOPorts),
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2016-08-10 07:19:08 +02:00
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start = BigInt("50000000", 16),
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collapse = true)
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2016-06-04 02:29:05 +02:00
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lazy val globalAddrMap = {
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val memBase = 0x80000000L
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2016-08-18 01:31:34 +02:00
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val memSize = site(ExtMemSize)
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2016-08-10 03:26:52 +02:00
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val intern = AddrMapEntry("int", internalIOAddrMap)
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2016-08-10 07:19:08 +02:00
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val extern = AddrMapEntry("ext", externalAddrMap)
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2016-09-03 00:59:16 +02:00
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val io = AddrMapEntry("io", AddrMap((intern +: site(ExportMMIOPort).option(extern).toSeq):_*))
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val mem = AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))
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val addrMap = AddrMap((io +: (site(NMemoryChannels) > 0).option(mem).toSeq):_*)
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2016-05-01 05:59:36 +02:00
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2016-09-03 00:59:16 +02:00
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Dump("MEM_BASE", memBase)
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2016-06-04 02:29:05 +02:00
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addrMap
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2016-04-29 01:15:31 +02:00
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}
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2016-03-15 02:03:33 +01:00
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def makeConfigString() = {
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2016-06-04 02:29:05 +02:00
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val addrMap = globalAddrMap
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2016-06-06 13:51:55 +02:00
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val plicAddr = addrMap("io:int:plic").start
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val prciAddr = addrMap("io:int:prci").start
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2016-05-10 09:27:31 +02:00
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val plicInfo = site(PLICKey)
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2016-03-15 02:03:33 +01:00
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val xLen = site(XLen)
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val res = new StringBuilder
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2016-05-10 09:27:31 +02:00
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res append "plic {\n"
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res append s" priority 0x${plicAddr.toString(16)};\n"
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res append s" pending 0x${(plicAddr + plicInfo.pendingBase).toString(16)};\n"
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res append s" ndevs ${plicInfo.nDevices};\n"
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res append "};\n"
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2016-04-27 23:57:54 +02:00
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res append "rtc {\n"
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2016-06-28 08:08:29 +02:00
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res append s" addr 0x${(prciAddr + PRCI.time).toString(16)};\n"
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2016-04-27 23:57:54 +02:00
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res append "};\n"
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2016-09-03 00:59:16 +02:00
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if (addrMap contains "mem") {
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res append "ram {\n"
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res append " 0 {\n"
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res append s" addr 0x${addrMap("mem").start.toString(16)};\n"
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res append s" size 0x${addrMap("mem").size.toString(16)};\n"
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res append " };\n"
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res append "};\n"
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}
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2016-09-06 19:40:11 +02:00
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res append "core {\n"
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2016-09-03 00:59:16 +02:00
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for (i <- 0 until site(NTiles)) { // TODO heterogeneous tiles
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2016-09-07 08:53:12 +02:00
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val isa = {
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val m = if (site(MulDivKey).nonEmpty) "m" else ""
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val a = if (site(UseAtomics)) "a" else ""
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val f = if (site(FPUKey).nonEmpty) "f" else ""
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val d = if (site(FPUKey).nonEmpty && site(XLen) > 32) "d" else ""
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val s = if (site(UseVM)) "s" else ""
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s"rv${site(XLen)}i$m$a$f$d$s"
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}
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2016-03-15 02:03:33 +01:00
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res append s" $i {\n"
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res append " 0 {\n"
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2016-04-29 01:15:31 +02:00
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res append s" isa $isa;\n"
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2016-06-28 08:08:29 +02:00
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res append s" timecmp 0x${(prciAddr + PRCI.timecmp(i)).toString(16)};\n"
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res append s" ipi 0x${(prciAddr + PRCI.msip(i)).toString(16)};\n"
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2016-05-10 09:27:31 +02:00
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res append s" plic {\n"
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res append s" m {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'M')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'M')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'M')).toString(16)};\n"
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res append s" };\n"
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2016-05-13 20:22:46 +02:00
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if (site(UseVM)) {
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res append s" s {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'S')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'S')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n"
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res append s" };\n"
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}
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2016-09-06 19:40:11 +02:00
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res append " };\n"
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2016-03-15 02:03:33 +01:00
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res append " };\n"
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res append " };\n"
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}
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2016-08-11 19:44:32 +02:00
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res append "};\n"
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2016-08-20 03:26:34 +02:00
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res append (site(ExtraDevices).makeConfigString(addrMap))
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2016-03-15 02:03:33 +01:00
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res append '\u0000'
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res.toString.getBytes
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2015-09-25 18:41:19 +02:00
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}
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2016-07-01 03:20:43 +02:00
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lazy val innerDataBits = 64
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2016-06-08 19:16:04 +02:00
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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2014-10-06 22:43:40 +02:00
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pname match {
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//Memory Parameters
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2016-05-08 06:26:03 +02:00
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case MIFTagBits => Dump("MIF_TAG_BITS", 5)
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2016-02-27 20:41:28 +01:00
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case MIFDataBits => Dump("MIF_DATA_BITS", 64)
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2016-02-26 10:29:38 +01:00
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case MIFAddrBits => Dump("MIF_ADDR_BITS",
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site(PAddrBits) - site(CacheBlockOffsetBits))
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2015-10-13 21:46:23 +02:00
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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2015-10-14 20:33:18 +02:00
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case NastiKey => {
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Dump("MEM_STRB_BITS", site(MIFDataBits) / 8)
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NastiParameters(
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dataBits = Dump("MEM_DATA_BITS", site(MIFDataBits)),
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addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
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idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
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}
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2016-08-10 03:26:52 +02:00
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case BuildCoreplex => (p: Parameters) => Module(new DefaultCoreplex(p))
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2016-08-25 19:04:31 +02:00
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case NExtTopInterrupts => 2
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2016-08-26 19:09:03 +02:00
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case NExtPeripheryInterrupts => site(ExtraDevices).nInterrupts
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2016-08-25 19:04:31 +02:00
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// Note that PLIC asserts that this is > 0.
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case NExtInterrupts => site(NExtTopInterrupts) + site(NExtPeripheryInterrupts)
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2016-08-11 02:20:00 +02:00
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case AsyncDebugBus => false
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2016-08-19 18:46:43 +02:00
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case IncludeJtagDTM => false
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2016-07-18 23:09:10 +02:00
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case AsyncMMIOChannels => false
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2016-08-20 03:26:34 +02:00
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case ExtraDevices => new EmptyDeviceBlock
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2016-08-04 21:42:07 +02:00
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case ExtraTopPorts => (p: Parameters) => new Bundle
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2016-08-10 03:26:52 +02:00
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case ExtMMIOPorts => Nil
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2016-05-26 23:14:56 +02:00
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case NExtMMIOAXIChannels => 0
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2016-05-26 23:49:27 +02:00
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case NExtMMIOAHBChannels => 0
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2016-07-01 03:20:43 +02:00
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case NExtMMIOTLChannels => 0
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2016-09-07 09:05:00 +02:00
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case ExportMMIOPort => !externalAddrMap.isEmpty
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2016-07-18 23:09:10 +02:00
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case AsyncBusChannels => false
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2016-07-05 21:43:33 +02:00
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case NExtBusAXIChannels => 0
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2016-08-20 03:57:34 +02:00
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case NExternalClients => (if (site(NExtBusAXIChannels) > 0) 1 else 0) +
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2016-08-20 03:26:34 +02:00
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site(ExtraDevices).nClientPorts
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2016-08-11 02:20:00 +02:00
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case ConnectExtraPorts =>
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(out: Bundle, in: Bundle, p: Parameters) => out <> in
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2016-05-25 00:59:59 +02:00
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case HastiId => "Ext"
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2016-05-25 00:59:59 +02:00
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case HastiKey("TL") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
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2016-05-25 00:59:59 +02:00
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case HastiKey("Ext") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(XLen))
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2016-07-18 23:09:10 +02:00
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case AsyncMemChannels => false
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2015-10-31 05:14:33 +01:00
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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2016-06-02 00:00:48 +02:00
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case TMemoryChannels => BusType.AXI
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2016-08-18 01:31:34 +02:00
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case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
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2016-03-15 02:03:33 +01:00
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case ConfigString => makeConfigString()
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2016-04-29 01:15:31 +02:00
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case GlobalAddrMap => globalAddrMap
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2016-09-02 20:11:40 +02:00
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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2016-09-03 00:14:39 +02:00
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case RTCTick => (p: Parameters, t_io: Bundle, p_io:Bundle) => Counter(p(RTCPeriod)).inc()
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2016-06-08 01:13:01 +02:00
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case _ => throw new CDEMatchError
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2016-08-11 02:20:00 +02:00
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}})
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2015-12-16 19:24:57 +01:00
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2016-08-11 02:20:00 +02:00
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class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
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class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
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2015-11-21 08:26:28 +01:00
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2016-05-25 20:08:11 +02:00
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class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
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2016-07-05 02:07:58 +02:00
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class DefaultBufferlessConfig extends Config(
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new WithBufferlessBroadcastHub ++ new BaseConfig)
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2015-10-22 03:23:58 +02:00
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class FPGAConfig extends Config (
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2014-10-06 22:43:40 +02:00
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(pname,site,here) => pname match {
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2015-07-31 01:30:00 +02:00
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case NAcquireTransactors => 4
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2016-07-11 21:17:29 +02:00
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case ExportGroundTestStatus => true
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2016-06-08 01:13:01 +02:00
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case _ => throw new CDEMatchError
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2014-09-24 02:05:14 +02:00
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}
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2014-10-06 22:43:40 +02:00
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)
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2014-09-24 02:05:14 +02:00
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2016-08-11 02:20:00 +02:00
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class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
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class DefaultL2FPGAConfig extends Config(
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new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
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class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
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class WithNMemoryChannels(n: Int) extends Config(
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(pname,site,here) => pname match {
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case NMemoryChannels => Dump("N_MEM_CHANNELS", n)
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2016-06-08 01:13:01 +02:00
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case _ => throw new CDEMatchError
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2016-05-25 20:08:11 +02:00
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}
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)
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2016-08-18 01:31:34 +02:00
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class WithExtMemSize(n: Long) extends Config(
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(pname,site,here) => pname match {
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case ExtMemSize => Dump("MEM_SIZE", n)
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case _ => throw new CDEMatchError
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}
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)
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2016-06-02 01:18:42 +02:00
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class WithAHB extends Config(
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(pname, site, here) => pname match {
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case TMemoryChannels => BusType.AHB
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case NExtMMIOAHBChannels => 1
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})
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2016-07-01 03:20:43 +02:00
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class WithTL extends Config(
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(pname, site, here) => pname match {
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case TMemoryChannels => BusType.TL
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case NExtMMIOTLChannels => 1
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})
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2016-09-03 00:59:16 +02:00
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class WithScratchpads extends Config(new WithNMemoryChannels(0) ++ new WithDataScratchpad(16384))
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2016-06-23 01:08:27 +02:00
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class DefaultFPGASmallConfig extends Config(new WithSmallCores ++ new DefaultFPGAConfig)
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class DefaultSmallConfig extends Config(new WithSmallCores ++ new BaseConfig)
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class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultSmallConfig)
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2015-08-06 21:51:18 +02:00
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2016-06-14 01:24:01 +02:00
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class DualBankConfig extends Config(
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new WithNBanksPerMemChannel(2) ++ new BaseConfig)
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2015-11-19 02:07:01 +01:00
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class DualBankL2Config extends Config(
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2016-06-14 01:24:01 +02:00
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new WithNBanksPerMemChannel(2) ++ new WithL2Cache ++ new BaseConfig)
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2015-11-03 05:10:10 +01:00
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2016-06-14 01:24:01 +02:00
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class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new BaseConfig)
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2015-11-19 02:07:01 +01:00
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class DualChannelL2Config extends Config(
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2016-06-14 01:24:01 +02:00
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new WithNMemoryChannels(2) ++ new WithL2Cache ++ new BaseConfig)
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2015-11-19 02:07:01 +01:00
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class DualChannelDualBankConfig extends Config(
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2016-06-14 01:24:01 +02:00
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new WithNMemoryChannels(2) ++
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new WithNBanksPerMemChannel(2) ++ new BaseConfig)
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2015-11-19 02:07:01 +01:00
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class DualChannelDualBankL2Config extends Config(
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2016-06-14 01:24:01 +02:00
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(2) ++
|
2016-05-25 20:08:11 +02:00
|
|
|
new WithL2Cache ++ new BaseConfig)
|
2015-11-19 02:07:01 +01:00
|
|
|
|
2016-05-25 20:08:11 +02:00
|
|
|
class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
|
2015-11-21 08:26:28 +01:00
|
|
|
|
2016-07-01 03:20:43 +02:00
|
|
|
class WithMIFDataBits(n: Int) extends Config(
|
|
|
|
(pname, site, here) => pname match {
|
|
|
|
case MIFDataBits => Dump("MIF_DATA_BITS", n)
|
|
|
|
})
|
|
|
|
|
|
|
|
class MIF128BitConfig extends Config(
|
|
|
|
new WithMIFDataBits(128) ++ new BaseConfig)
|
2016-07-02 03:13:33 +02:00
|
|
|
class MIF32BitConfig extends Config(
|
|
|
|
new WithMIFDataBits(32) ++ new BaseConfig)
|
2016-07-01 03:20:43 +02:00
|
|
|
|
2015-11-21 08:26:28 +01:00
|
|
|
class SmallL2Config extends Config(
|
2016-06-14 01:24:01 +02:00
|
|
|
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
|
|
|
|
new WithL2Capacity(256) ++ new DefaultL2Config)
|
2016-01-07 06:38:35 +01:00
|
|
|
|
2016-06-14 01:24:01 +02:00
|
|
|
class SingleChannelBenchmarkConfig extends Config(new WithL2Capacity(256) ++ new DefaultL2Config)
|
|
|
|
class DualChannelBenchmarkConfig extends Config(new WithNMemoryChannels(2) ++ new SingleChannelBenchmarkConfig)
|
|
|
|
class QuadChannelBenchmarkConfig extends Config(new WithNMemoryChannels(4) ++ new SingleChannelBenchmarkConfig)
|
|
|
|
class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ new SingleChannelBenchmarkConfig)
|
2016-02-18 00:23:30 +01:00
|
|
|
|
2016-06-14 01:24:01 +02:00
|
|
|
class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig)
|
2016-02-26 10:33:25 +01:00
|
|
|
|
2016-02-29 23:49:18 +01:00
|
|
|
class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
|
2016-03-28 22:22:00 +02:00
|
|
|
|
2016-06-21 02:58:26 +02:00
|
|
|
class DualCoreConfig extends Config(
|
|
|
|
new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig)
|
2016-07-22 20:36:45 +02:00
|
|
|
|
|
|
|
class TinyConfig extends Config(
|
2016-09-03 00:59:16 +02:00
|
|
|
new WithScratchpads ++
|
2016-09-07 08:53:12 +02:00
|
|
|
new WithSmallCores ++ new WithRV32 ++
|
2016-07-22 20:36:45 +02:00
|
|
|
new WithStatelessBridge ++ new BaseConfig)
|
2016-08-04 01:33:30 +02:00
|
|
|
|
|
|
|
class WithTestRAM extends Config(
|
|
|
|
(pname, site, here) => pname match {
|
2016-08-04 21:42:07 +02:00
|
|
|
case ExtraDevices => {
|
2016-08-20 03:26:34 +02:00
|
|
|
class TestRAMDevice extends DeviceBlock {
|
2016-08-04 21:42:07 +02:00
|
|
|
val ramSize = 0x1000
|
2016-08-20 03:26:34 +02:00
|
|
|
def nClientPorts = 0
|
|
|
|
def addrMapEntries = Seq(
|
|
|
|
AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW))))
|
2016-08-18 21:14:41 +02:00
|
|
|
def builder(
|
2016-08-25 19:04:31 +02:00
|
|
|
mmioPorts: HashMap[String, ClientUncachedTileLinkIO],
|
|
|
|
clientPorts: Seq[ClientUncachedTileLinkIO],
|
|
|
|
interrupts: Seq[Bool],
|
|
|
|
extra: Bundle, p: Parameters) {
|
2016-08-04 21:42:07 +02:00
|
|
|
val testram = Module(new TileLinkTestRAM(ramSize)(p))
|
2016-08-20 03:26:34 +02:00
|
|
|
testram.io <> mmioPorts("testram")
|
2016-08-04 21:42:07 +02:00
|
|
|
}
|
|
|
|
}
|
2016-08-20 03:26:34 +02:00
|
|
|
new TestRAMDevice
|
2016-08-04 21:42:07 +02:00
|
|
|
}
|
2016-08-19 18:46:43 +02:00
|
|
|
}
|
|
|
|
)
|
|
|
|
|
|
|
|
class WithAsyncDebug extends Config (
|
|
|
|
(pname, site, here) => pname match {
|
|
|
|
case AsyncDebugBus => true
|
|
|
|
}
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
|
|
class WithJtagDTM extends Config (
|
|
|
|
(pname, site, here) => pname match {
|
|
|
|
case IncludeJtagDTM => true
|
|
|
|
}
|
|
|
|
)
|