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cc6631ae4d
reset -> _reset
Huy Vo
2013-08-12 20:52:55 -07:00
d5c9eb0f54
reset -> resetVal, getReset -> reset
Huy Vo
2013-08-12 20:52:18 -07:00
387cf0ebe0
reset -> resetVal, getReset -> reset
Huy Vo
2013-08-12 20:51:54 -07:00
11e131af47
initial attempt at upgrade
Henry Cook
2013-08-12 10:46:22 -07:00
1a9e43aa11
initial attempt at upgrade
Henry Cook
2013-08-12 10:39:11 -07:00
5c7a1f5cd6
initial attempt at upgrade
Henry Cook
2013-08-12 10:36:44 -07:00
199e76fc77
Fold uncore constants into TileLinkConfiguration, update coherence API
Henry Cook
2013-08-02 15:02:09 -07:00
de313d97de
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
Henry Cook
2013-08-02 16:30:09 -07:00
4eaab214d2
Fold uncore constants into TileLinkConfiguration, update coherence API
Henry Cook
2013-08-02 14:54:16 -07:00
bef6c1db35
minor nbdcache cleanup
Henry Cook
2013-08-02 10:06:01 -07:00
bc2b45da12
Fold uncore constants into TileLinkConfiguration, update coherence API
Henry Cook
2013-08-02 14:55:06 -07:00
c1b1a21a0f
If +stats is set when running simv-debug, will only output vcd data when cr28 is high.
Stephen Twigg
2013-07-30 16:39:47 -07:00
3132db4f90
Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.
Stephen Twigg
2013-07-30 16:36:28 -07:00
4d916b56e3
Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file.
Henry Cook
2013-07-24 23:28:43 -07:00
d8440b042a
Make compatible with scala 2.10. Refactor constants into package object. Remove networking primitives from package object. Clean up request generators. Chnage ++ to +: for appending to io.incoherent.
Henry Cook
2013-07-24 23:22:36 -07:00
9abdf4e154
Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
Henry Cook
2013-07-23 20:26:17 -07:00
3f874342a4
Update chisel to appropriate version for reference chip build.
Stephen Twigg
2013-07-10 17:08:56 -07:00
c7bf1aaac9
Merge branch 'master' of github.com:ucb-bar/reference-chip
Ben Keller
2013-07-10 16:01:25 -07:00
a72e0dc99e
Updated riscv-tools reference
Ben Keller
2013-07-10 16:01:01 -07:00
2796de01bf
new tilelink arbiter types, reduced release xact trackers
Henry Cook
2013-07-09 15:41:27 -07:00
db8e5fda9b
new tilelink arbiter types, reduced release xact trackers
Henry Cook
2013-07-09 15:37:42 -07:00
5c00d0a030
new tilelink arbiter type
Henry Cook
2013-07-09 15:31:39 -07:00
c5f01f3f87
update rocket
Andrew Waterman
2013-06-15 00:55:34 -07:00
7cc53c7725
clean up Str
Andrew Waterman
2013-06-15 00:45:53 -07:00
4ae0c68303
require -std=c++11, as -std=c++0x doesn't cut it
Andrew Waterman
2013-06-14 00:27:52 -07:00
896179cbb6
removed bad mt test
Henry Cook
2013-06-14 00:14:18 -07:00
85fbb650c9
makefile support for new multithreading tests
Henry Cook
2013-06-13 15:34:15 -07:00
ae0716fb6d
Use chisel printf for logging
Andrew Waterman
2013-06-13 10:53:23 -07:00
95c5147dc5
Add RISC-V instruction disassembler
Andrew Waterman
2013-06-13 10:31:04 -07:00
bd43ca8423
Merge branch 'master' of github.com:ucb-bar/reference-chip
Stephen Twigg
2013-05-23 17:51:24 -07:00
c06cbf523b
Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore.
Henry Cook
2013-05-23 14:55:59 -07:00
6a69d7d7b5
pass closure to generate bank addr
Henry Cook
2013-04-22 17:38:13 -07:00
9631b6081e
Merge branch 'tilelink-data'
Henry Cook
2013-05-23 14:53:10 -07:00
cf02f1ef01
use new locking round robin arbiter
Henry Cook
2013-04-22 16:48:55 -07:00
569d8fd796
Merge branch 'tilelink-data'
Henry Cook
2013-05-23 14:14:40 -07:00
12205b9684
remove obsolete config file reader prototype
Henry Cook
2013-05-23 14:09:03 -07:00
fe9adfe71b
Simplify and correct integer multiplier
Andrew Waterman
2013-05-21 19:35:08 -07:00
26ed805862
push chisel,riscv-rocket,uncore
Yunsup Lee
2013-05-21 18:59:57 -07:00
11133d6d4c
clock gate s2 registers in the frontend
Yunsup Lee
2013-05-21 18:59:21 -07:00
c837c1d800
fix bug in previous JALR commit
Yunsup Lee
2013-05-21 18:28:44 -07:00
69b508ff39
ported caches and htif to use new tilelink
Henry Cook
2013-05-21 17:21:04 -07:00
4c1f105ce9
added PairedData link type with matching crossbar, ported tilelink and uncore to use
Henry Cook
2013-05-21 17:19:07 -07:00
28f914c3f2
don't JALR to speculatively-bypassed addresses
Andrew Waterman
2013-05-21 16:53:47 -07:00
dcde377303
Fix DM I$ deadlock
Yunsup Lee
2013-05-20 15:22:58 -07:00
3a1b5f01b2
don't take interrupts while they're disabled!
Andrew Waterman
2013-05-19 23:27:47 -07:00
6eb4c2542a
comment out I$ assert for now
Andrew Waterman
2013-05-18 18:09:23 -07:00
1dab984231
use UFix instead of Bits for arithmetic
Andrew Waterman
2013-05-18 00:45:29 -07:00
dfa7a03f73
use assert, not Assert
Andrew Waterman
2013-05-18 00:45:13 -07:00
f3c78abc2b
push riscv-tests
Yunsup Lee
2013-05-16 00:51:02 -07:00
e77bde71d0
push riscv-tools
Yunsup Lee
2013-05-15 12:03:52 -07:00
f0b0867f5a
push riscv-tests
Yunsup Lee
2013-05-13 19:22:28 -07:00
f13605d2f5
push riscv-tools
Yunsup Lee
2013-05-13 19:14:57 -07:00
7ba3ab03e2
update README
Yunsup Lee
2013-05-13 11:19:55 -07:00
5b55cc93af
add submodule riscv-tools
Yunsup Lee
2013-05-10 11:53:55 -07:00
0672773c1a
for now, don't use asserts outside of components
Andrew Waterman
2013-05-09 02:14:44 -07:00
e8fcdb56a6
update chisel to work around xilinx ise bug
Andrew Waterman
2013-05-03 01:47:15 -07:00
d825c9d6e9
make fpga Makefile work with updated Makefrag
Andrew Waterman
2013-05-02 05:09:45 -07:00
cfa86dba4f
add FPGA test bench
Andrew Waterman
2013-05-02 04:58:43 -07:00
d2e1828714
gracefully kill htif thread, fixing tty stuff
Andrew Waterman
2013-05-01 21:11:05 -07:00
d405ffa949
assume all I$ grants bear data
Andrew Waterman
2013-05-01 21:01:20 -07:00
9a3b2e7006
new paired meta/data IO type, and matching arbiter
Henry Cook
2013-05-01 16:48:01 -07:00
474d321cc7
fix meta hazard counter to reset on new meta writes
Andrew Waterman
2013-05-01 16:35:24 -07:00
a6a88fce19
Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle"
Andrew Waterman
2013-05-01 16:34:45 -07:00
63a38e7982
Revert "temp"
Andrew Waterman
2013-05-01 16:34:33 -07:00
b6945408cb
temp
Henry Cook
2013-05-01 10:24:36 -07:00
722bc917d3
broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle
Henry Cook
2013-05-01 10:05:54 -07:00
a86ad08c1e
commit awesome vlsi/energy scripts
Yunsup Lee
2013-05-01 02:58:53 -07:00
50bd9a08a7
resynchronize fpga uncore
Andrew Waterman
2013-05-01 01:12:47 -07:00
9a258e7fb4
use new locking round robin arbiter
Henry Cook
2013-04-22 16:48:55 -07:00
fedc2753e4
make sure master_xact_id field is large enough for temporary extra release trackers
Henry Cook
2013-04-30 11:00:23 -07:00
1501e90c1f
interlock probe unit on tag RAW hazards
Andrew Waterman
2013-04-30 00:37:51 -07:00
a2f584e928
add riscv-tests, get rid of riscv-asmtests-bmarks
Yunsup Lee
2013-04-29 19:29:51 -07:00
12d394811e
Allow release data to be written out even before all releases have been collected
Henry Cook
2013-04-29 18:47:37 -07:00
e8b20f3d38
clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant
Henry Cook
2013-04-25 17:37:04 -07:00
7fe052e1bf
update README
Yunsup Lee
2013-04-24 02:05:28 -07:00
9114012def
assmebly tests are now built from riscv-tests
Yunsup Lee
2013-04-24 01:59:14 -07:00
93df795e48
change LLC leaf SRAM size
Yunsup Lee
2013-04-22 11:06:31 -07:00
7f5282d355
replace RDNPC with AUIPC
Andrew Waterman
2013-04-22 04:21:46 -07:00
50ccc20bf3
replace RDNPC with AUIPC
Andrew Waterman
2013-04-22 04:20:15 -07:00
2ac3fd5306
get rid of init_node
Huy Vo
2013-04-20 01:36:32 -07:00
0d87e3bacc
fixed init pin generation
Huy Vo
2013-04-20 00:38:01 -07:00
a01cdf95fd
tell physical networks carring cache lines to lock arbitration for REFILL_CYCLES pumps
Henry Cook
2013-04-10 13:53:27 -07:00
db5a060c7d
fix io dir
Henry Cook
2013-04-10 13:47:30 -07:00
766d5622b1
Prevent messages from becoming interleaved in the BasicCrossbar. Remove dependency trackers from the uncore, use msg headers instead. Have one ReleaseHnadler per core for now.
Henry Cook
2013-04-10 13:46:31 -07:00
d7982bf27f
bump uncore for grant fix
Henry Cook
2013-04-09 14:28:54 -07:00
74187c2068
Always route voluntary releases to ReleaseTracker to ensure all grants are sent
Henry Cook
2013-04-09 14:09:36 -07:00
7ea782fd22
add LR/SC
Andrew Waterman
2013-04-07 19:35:51 -07:00
ae7720e284
guarantee LR/SC forward progress
Andrew Waterman
2013-04-07 19:27:21 -07:00
7ff5b5b86f
treat load-reserved as a non-dirtying store
Andrew Waterman
2013-04-07 19:23:44 -07:00
3479f1c6cd
add LR/SC support
Andrew Waterman
2013-04-03 22:13:51 -07:00
e74e032c87
simplify MSHR memory response logic
Andrew Waterman
2013-04-06 01:03:37 -07:00
1abb9277db
fix LR/SC atomicity violation
Andrew Waterman
2013-04-05 19:13:38 -07:00
8cbdeb2abf
add LR/SC support
Andrew Waterman
2013-04-03 22:15:39 -07:00
fc46daecf6
don't flush pipeline on writes to side-effect-free PCRs
Andrew Waterman
2013-04-02 17:37:21 -07:00
8b439ef20d
only support setpcr/clearpcr of SR
Andrew Waterman
2013-04-02 14:43:01 -07:00
d43f484feb
take interrupts on nonzero fromhost values
Andrew Waterman
2013-03-25 23:27:23 -07:00
d4a3351cfc
expose pending interrupts in status register
Andrew Waterman
2013-03-25 23:26:47 -07:00
c6b56c5f25
bump rocket for coherence bug fix
Henry Cook
2013-04-04 15:51:24 -07:00
f8aebcbf8c
fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match
Henry Cook
2013-04-04 15:50:29 -07:00
9d5e97d89e
override io in LogicalNetwork
Henry Cook
2013-03-28 14:10:20 -07:00