Merge branch 'tilelink-data'
Conflicts: src/package.scala
This commit is contained in:
Henry Cook
commit
9631b6081e
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@ -3,9 +3,9 @@ package uncore
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import Chisel._
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import Constants._
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trait CoherenceAgentRole
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trait ClientCoherenceAgent extends CoherenceAgentRole
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trait MasterCoherenceAgent extends CoherenceAgentRole
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abstract trait CoherenceAgentRole
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abstract trait ClientCoherenceAgent extends CoherenceAgentRole
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abstract trait MasterCoherenceAgent extends CoherenceAgentRole
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abstract class CoherencePolicy {
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def isHit (cmd: Bits, state: UFix): Bool
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@ -8,6 +8,100 @@ import scala.collection.mutable.Stack
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implicit def toOption[A](a: A) = Option(a)
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class PairedDataIO[M <: Data, D <: Data]()(m: => M, d: => D) extends Bundle {
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val meta = new FIFOIO()(m)
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val data = new FIFOIO()(d)
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override def clone = { new PairedDataIO()(m,d).asInstanceOf[this.type] }
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}
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class PairedArbiterIO[M <: Data, D <: Data](n: Int)(m: => M, d: => D) extends Bundle {
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val in = Vec(n) { new PairedDataIO()(m,d) }.flip
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val out = new PairedDataIO()(m,d)
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val meta_chosen = Bits(OUTPUT, log2Up(n))
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val data_chosen = Bits(OUTPUT, log2Up(n))
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override def clone = { new PairedArbiterIO(n)(m,d).asInstanceOf[this.type] }
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}
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class PairedLockingRRArbiter[M <: Data, D <: Data](n: Int, count: Int, needsLock: Option[M => Bool] = None)(meta: => M, data: => D) extends Component {
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require(isPow2(count))
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val io = new PairedArbiterIO(n)(meta,data)
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val locked = if(count > 1) Reg(resetVal = Bool(false)) else Bool(false)
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val lockIdx = if(count > 1) Reg(resetVal = UFix(n-1)) else UFix(n-1)
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val grant = List.fill(n)(Bool())
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val meta_chosen = Bits(width = log2Up(n))
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val chosen_meta_has_data = needsLock.map(_(io.in(meta_chosen).meta.bits)).getOrElse(Bool(true))
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val valid_meta_has_data = io.in(meta_chosen).meta.valid && chosen_meta_has_data
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val grant_chosen_meta = !(locked && chosen_meta_has_data)
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(0 until n).map(i => io.in(i).meta.ready := grant(i) && grant_chosen_meta && io.out.meta.ready)
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(0 until n).map(i => io.in(i).data.ready := Mux(locked, lockIdx === UFix(i), grant(i) && valid_meta_has_data) && io.out.data.ready)
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io.out.meta.valid := io.in(meta_chosen).meta.valid && grant_chosen_meta
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io.out.data.valid := Mux(locked, io.in(lockIdx).data.valid, io.in(meta_chosen).data.valid && valid_meta_has_data)
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io.out.meta.bits := io.in(meta_chosen).meta.bits
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io.out.data.bits := Mux(locked, io.in(lockIdx).data.bits, io.in(meta_chosen).data.bits)
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io.meta_chosen := meta_chosen
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io.data_chosen := Mux(locked, lockIdx, meta_chosen)
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if(count > 1){
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val cnt = Reg(resetVal = UFix(0, width = log2Up(count)))
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val cnt_next = cnt + UFix(1)
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when(io.out.data.fire()){
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cnt := cnt_next
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when(cnt_next === UFix(0)) {
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locked := Bool(false)
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}
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}
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when(io.out.meta.fire()) {
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when(needsLock.map(_(io.out.meta.bits)).getOrElse(Bool(true))) {
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when(!locked) {
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locked := Bool(true)
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lockIdx := Vec(io.in.map{in => in.meta.fire()}){Bool()}.indexWhere{i: Bool => i}
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}
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}
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}
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}
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val last_grant = Reg(resetVal = Bits(0, log2Up(n)))
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val ctrl = ArbiterCtrl((0 until n).map(i => io.in(i).meta.valid && UFix(i) > last_grant) ++ io.in.map(_.meta.valid))
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(0 until n).map(i => grant(i) := ctrl(i) && UFix(i) > last_grant || ctrl(i + n))
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var choose = Bits(n-1)
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for (i <- n-2 to 0 by -1)
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choose = Mux(io.in(i).meta.valid, Bits(i), choose)
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for (i <- n-1 to 1 by -1)
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choose = Mux(io.in(i).meta.valid && UFix(i) > last_grant, Bits(i), choose)
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meta_chosen := choose
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when (io.out.meta.fire()) { last_grant := meta_chosen }
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}
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class PairedCrossbar[M <: Data, D <: Data](count: Int, needsLock: Option[BasicCrossbarIO[M] => Bool] = None)(meta: => M, data: => D)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
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val io = new Bundle {
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val in = Vec(conf.nEndpoints){new PairedDataIO()(new BasicCrossbarIO()(meta),new BasicCrossbarIO()(data))}.flip
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val out = Vec(conf.nEndpoints){new PairedDataIO()(new BasicCrossbarIO()(meta),new BasicCrossbarIO()(data))}
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}
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val metaRdyVecs = List.fill(conf.nEndpoints)(Vec(conf.nEndpoints){Bool()})
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val dataRdyVecs = List.fill(conf.nEndpoints)(Vec(conf.nEndpoints){Bool()})
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val rdyVecs = metaRdyVecs zip dataRdyVecs
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io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
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val rrarb = new PairedLockingRRArbiter(conf.nEndpoints, count, needsLock)(io.in(0).meta.bits.clone, io.in(0).data.bits.clone)
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rrarb.io.in zip io.in zip rdys._1 zip rdys._2 map { case (((arb, in), meta_rdy), data_rdy) => {
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arb.meta.valid := in.meta.valid && (in.meta.bits.header.dst === UFix(i))
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arb.meta.bits := in.meta.bits
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meta_rdy := arb.meta.ready && (in.meta.bits.header.dst === UFix(i))
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arb.data.valid := in.data.valid && (in.data.bits.header.dst === UFix(i))
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arb.data.bits := in.data.bits
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data_rdy := arb.data.ready && (in.data.bits.header.dst === UFix(i))
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}}
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out <> rrarb.io.out
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}}
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for(i <- 0 until conf.nEndpoints) {
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io.in(i).meta.ready := rdyVecs.map(r => r._1(i)).reduceLeft(_||_)
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io.in(i).data.ready := rdyVecs.map(r => r._2(i)).reduceLeft(_||_)
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}
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}
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case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
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class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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@ -26,7 +120,7 @@ class BasicCrossbarIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkCon
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abstract class PhysicalNetwork(conf: PhysicalNetworkConfiguration) extends Component
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class BasicCrossbar[T <: Data](count: Int)(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
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class BasicCrossbar[T <: Data](count: Int = 1)(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
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val io = new Bundle {
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val in = Vec(conf.nEndpoints){(new FIFOIO){(new BasicCrossbarIO){data}}}.flip
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val out = Vec(conf.nEndpoints){(new FIFOIO){(new BasicCrossbarIO){data}}}
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@ -116,82 +116,55 @@ class Grant extends MasterSourcedMessage with HasMemData with HasClientTransacti
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class GrantAck extends ClientSourcedMessage with HasMasterTransactionId
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abstract class DirectionalFIFOIO[T <: Data]()(data: => T) extends FIFOIO()(data)
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class ClientSourcedIO[T <: Data]()(data: => T) extends DirectionalFIFOIO()(data)
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class ClientSourcedDataIO[T <: Data]()(data: => T) extends ClientSourcedIO()(data)
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class MasterSourcedIO[T <: Data]()(data: => T) extends DirectionalFIFOIO()(data) {flip()}
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trait DirectionalIO
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trait ClientSourcedIO extends DirectionalIO
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trait MasterSourcedIO extends DirectionalIO
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class ClientSourcedFIFOIO[T <: Data]()(data: => T) extends FIFOIO()(data) with ClientSourcedIO {
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override def clone = { new ClientSourcedFIFOIO()(data).asInstanceOf[this.type] }
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}
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class ClientSourcedDataIO[M <: Data, D <: Data]()(meta: => M, data: => D) extends PairedDataIO()(meta,data) with ClientSourcedIO {
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override def clone = { new ClientSourcedDataIO()(meta,data).asInstanceOf[this.type] }
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}
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class MasterSourcedFIFOIO[T <: Data]()(data: => T) extends FIFOIO()(data) with MasterSourcedIO {
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flip()
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override def clone = { new MasterSourcedFIFOIO()(data).asInstanceOf[this.type] }
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}
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class MasterSourcedDataIO[M <: Data, D <: Data]()(meta: => M, data: => D) extends PairedDataIO()(meta,data) with MasterSourcedIO {
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flip()
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override def clone = { new MasterSourcedDataIO()(meta,data).asInstanceOf[this.type] }
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}
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class UncachedTileLinkIO(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val acquire = (new ClientSourcedIO){(new LogicalNetworkIO){new Acquire }}
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val acquire_data = (new ClientSourcedDataIO){(new LogicalNetworkIO){new AcquireData }}
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val grant = (new MasterSourcedIO) {(new LogicalNetworkIO){new Grant }}
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val grant_ack = (new ClientSourcedIO){(new LogicalNetworkIO){new GrantAck }}
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val acquire = new ClientSourcedDataIO()(new LogicalNetworkIO()(new Acquire), new LogicalNetworkIO()(new AcquireData))
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val grant = new MasterSourcedFIFOIO()(new LogicalNetworkIO()(new Grant))
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val grant_ack = new ClientSourcedFIFOIO()(new LogicalNetworkIO()(new GrantAck))
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override def clone = { new UncachedTileLinkIO().asInstanceOf[this.type] }
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}
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class TileLinkIO(implicit conf: LogicalNetworkConfiguration) extends UncachedTileLinkIO()(conf) {
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val probe = (new MasterSourcedIO){(new LogicalNetworkIO){new Probe }}
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val release = (new ClientSourcedIO){(new LogicalNetworkIO){new Release }}
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val release_data = (new ClientSourcedDataIO){(new LogicalNetworkIO){new ReleaseData }}
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val probe = new MasterSourcedFIFOIO()(new LogicalNetworkIO()(new Probe))
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val release = new ClientSourcedDataIO()(new LogicalNetworkIO()(new Release), new LogicalNetworkIO()(new ReleaseData))
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override def clone = { new TileLinkIO().asInstanceOf[this.type] }
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}
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object UncachedTileLinkIOArbiterShim {
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def apply[T <: HasClientTransactionId](in: ClientSourcedIO[LogicalNetworkIO[T]], id: Int, max: Int)(implicit lconf: LogicalNetworkConfiguration) = {
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val shim = (new UncachedTileLinkIOArbiterShim(id, max)){in.bits.payload.clone}
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shim.io.in <> in
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shim.io.out
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}
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}
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class UncachedTileLinkIOArbiterShim[T <: HasClientTransactionId](id: Int, max: Int)(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component {
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val io = new Bundle {
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val in = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}.flip
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val out = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}
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}
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io.out.bits := io.in.bits
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io.out.bits.payload.client_xact_id := Cat(io.in.bits.payload.client_xact_id, UFix(id, log2Up(max)))
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io.out.valid := io.in.valid
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io.in.ready := io.out.ready
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}
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class UncachedTileLinkIOArbiter(n: Int)(implicit conf: LogicalNetworkConfiguration) extends Component {
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class UncachedTileLinkIOArbiter(n: Int, co: CoherencePolicy)(implicit conf: LogicalNetworkConfiguration) extends Component {
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val io = new Bundle {
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val in = Vec(n) { new UncachedTileLinkIO }.flip
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val out = new UncachedTileLinkIO
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}
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val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
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val mem_cnt_next = mem_cnt + UFix(1)
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val locked = Reg(resetVal = Bool(false))
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val lock_idx = Reg(resetVal = UFix(n))
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when(io.out.acquire_data.valid && io.out.acquire_data.ready) {
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mem_cnt := mem_cnt_next
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when(!locked) {
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locked := Bool(true)
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lock_idx := Vec(io.in.map{ in => in.acquire_data.ready && in.acquire_data.valid}){Bool()}.indexWhere{i: Bool => i}
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}
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when(mem_cnt_next === UFix(0)) {
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locked := Bool(false)
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}
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}
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val acqd_grant = ArbiterCtrl(io.in.map(_.acquire_data.valid))
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(0 until n).map(i => io.in(i).acquire_data.ready := Mux(locked, UFix(i) === lock_idx, acqd_grant(i)) && io.out.acquire_data.ready)
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var acqd_bits = io.in(n-1).acquire_data.bits
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for (i <- n-2 to 0 by -1) {
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acqd_bits = Mux(io.in(i).acquire_data.valid, io.in(i).acquire_data.bits, acqd_bits)
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}
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val locked_req = io.in(lock_idx).acquire_data
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io.out.acquire_data.bits := Mux(locked, locked_req.bits, acqd_bits)
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io.out.acquire_data.valid := Mux(locked, locked_req.valid, io.in.map(_.acquire_data.valid).reduce(_||_))
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val acq_arb = (new Arbiter(n)){ (new LogicalNetworkIO){new Acquire} }
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def acqHasData(acq: LogicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
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val acq_arb = new PairedLockingRRArbiter(n, REFILL_CYCLES, acqHasData _)((new LogicalNetworkIO){new Acquire},(new LogicalNetworkIO){new AcquireData})
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io.out.acquire <> acq_arb.io.out
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io.in.map(_.acquire).zipWithIndex.map{ case(acq, id) => UncachedTileLinkIOArbiterShim(acq, id, n) }.zip(acq_arb.io.in).map{ case (req, arb) => req <> arb}
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io.in.map(_.acquire).zipWithIndex.zip(acq_arb.io.in).map{ case ((req,id), arb) => {
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arb.data <> req.data
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arb.meta.valid := req.meta.valid
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arb.meta.bits := req.meta.bits
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arb.meta.bits.payload.client_xact_id := Cat(req.meta.bits.payload.client_xact_id, UFix(id, log2Up(n)))
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req.meta.ready := arb.meta.ready
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}}
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val grant_ack_arb = (new Arbiter(n)){ (new LogicalNetworkIO){new GrantAck} }
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val grant_ack_arb = (new RRArbiter(n)){ (new LogicalNetworkIO){new GrantAck} }
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io.out.grant_ack <> grant_ack_arb.io.out
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grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack }
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@ -31,23 +31,22 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: UncoreConfiguration) extends
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// Handle acquire transaction initiation
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val acquire = io.client.acquire
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val acquire_data = io.client.acquire_data
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val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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val block_acquires = any_acquire_conflict
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val alloc_arb = (new Arbiter(trackerList.size)) { Bool() }
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.client
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alloc_arb.io.in(i).valid := t.acquire.ready
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t.acquire.bits := acquire.bits
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t.acquire.valid := alloc_arb.io.in(i).ready
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alloc_arb.io.in(i).valid := t.acquire.meta.ready
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t.acquire.meta.bits := acquire.meta.bits
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t.acquire.meta.valid := alloc_arb.io.in(i).ready
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t.acquire_data.bits := acquire_data.bits
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t.acquire_data.valid := acquire_data.valid
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t.acquire.data.bits := acquire.data.bits
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t.acquire.data.valid := acquire.data.valid
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}
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acquire.ready := trackerList.map(_.io.client.acquire.ready).reduce(_||_) && !block_acquires
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acquire_data.ready := trackerList.map(_.io.client.acquire_data.ready).reduce(_||_)
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alloc_arb.io.out.ready := acquire.valid && !block_acquires
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acquire.meta.ready := trackerList.map(_.io.client.acquire.meta.ready).reduce(_||_) && !block_acquires
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acquire.data.ready := trackerList.map(_.io.client.acquire.data.ready).reduce(_||_)
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alloc_arb.io.out.ready := acquire.meta.valid && !block_acquires
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// Handle probe request generation
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val probe_arb = (new Arbiter(trackerList.size)){(new LogicalNetworkIO){ new Probe }}
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@ -56,22 +55,21 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: UncoreConfiguration) extends
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// Handle releases, which might be voluntary and might have data
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val release = io.client.release
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val release_data = io.client.release_data
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val voluntary = co.isVoluntary(release.bits.payload)
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val voluntary = co.isVoluntary(release.meta.bits.payload)
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val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
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val block_releases = Bool(false)
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val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)){Bool()}.lastIndexWhere{b: Bool => b}
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//val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UFix(0)), release.bits.payload.master_xact_id) // TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
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val release_idx = Mux(voluntary, release.bits.header.src, release.bits.payload.master_xact_id)
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val release_idx = Mux(voluntary, release.meta.bits.header.src, release.meta.bits.payload.master_xact_id)
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.client
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t.release.bits := release.bits
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t.release.valid := release.valid && (release_idx === UFix(i)) && !block_releases
|
||||
t.release_data.bits := release_data.bits
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t.release_data.valid := release_data.valid
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t.release.meta.bits := release.meta.bits
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t.release.meta.valid := release.meta.valid && (release_idx === UFix(i)) && !block_releases
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t.release.data.bits := release.data.bits
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t.release.data.valid := release.data.valid
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}
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release.ready := Vec(trackerList.map(_.io.client.release.ready)){Bool()}(release_idx) && !block_releases
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release_data.ready := trackerList.map(_.io.client.release_data.ready).reduce(_||_)
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release.meta.ready := Vec(trackerList.map(_.io.client.release.meta.ready)){Bool()}(release_idx) && !block_releases
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release.data.ready := trackerList.map(_.io.client.release.data.ready).reduce(_||_)
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||||
// Reply to initial requestor
|
||||
val grant_arb = (new Arbiter(trackerList.size)){(new LogicalNetworkIO){ new Grant }}
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||||
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@ -85,7 +83,7 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: UncoreConfiguration) extends
|
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ack.ready := Bool(true)
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||||
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||||
// Create an arbiter for the one memory port
|
||||
val outer_arb = new UncachedTileLinkIOArbiter(trackerList.size)
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||||
val outer_arb = new UncachedTileLinkIOArbiter(trackerList.size, conf.co)
|
||||
outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.master }
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||||
io.master <> outer_arb.io.out
|
||||
}
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||||
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@ -114,22 +112,22 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: Uncore
|
|||
val cmd_to_read = co.getUncachedReadAcquire(xact.addr, UFix(trackerId))
|
||||
|
||||
io.has_acquire_conflict := Bool(false)
|
||||
io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.bits.payload.addr) && (state != s_idle)
|
||||
io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.meta.bits.payload.addr) && (state != s_idle)
|
||||
|
||||
io.master.grant.ready := Bool(false)
|
||||
io.master.acquire.valid := Bool(false)
|
||||
io.master.acquire.bits.payload := cmd_to_write
|
||||
io.master.acquire.meta.valid := Bool(false)
|
||||
io.master.acquire.meta.bits.payload := cmd_to_write
|
||||
//TODO io.master.acquire.bits.header.dst
|
||||
io.master.acquire.bits.header.src := UFix(bankId)
|
||||
io.master.acquire_data.valid := Bool(false)
|
||||
io.master.acquire_data.bits.payload.data := UFix(0)
|
||||
io.master.acquire.meta.bits.header.src := UFix(bankId)
|
||||
io.master.acquire.data.valid := Bool(false)
|
||||
io.master.acquire.data.bits.payload.data := UFix(0)
|
||||
//TODO io.master.acquire_data.bits.header.dst
|
||||
io.master.acquire_data.bits.header.src := UFix(bankId)
|
||||
io.client.acquire.ready := Bool(false)
|
||||
io.client.acquire_data.ready := Bool(false)
|
||||
io.master.acquire.data.bits.header.src := UFix(bankId)
|
||||
io.client.acquire.meta.ready := Bool(false)
|
||||
io.client.acquire.data.ready := Bool(false)
|
||||
io.client.probe.valid := Bool(false)
|
||||
io.client.release.ready := Bool(false)
|
||||
io.client.release_data.ready := Bool(false) // DNC
|
||||
io.client.release.meta.ready := Bool(false)
|
||||
io.client.release.data.ready := Bool(false) // DNC
|
||||
io.client.grant.valid := Bool(false)
|
||||
io.client.grant.bits.payload.g_type := co.getGrantType(xact, UFix(0))
|
||||
io.client.grant.bits.payload.client_xact_id := xact.client_xact_id
|
||||
|
|
@ -141,11 +139,11 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: Uncore
|
|||
|
||||
switch (state) {
|
||||
is(s_idle) {
|
||||
io.client.release.ready := Bool(true)
|
||||
when( io.client.release.valid ) {
|
||||
xact := io.client.release.bits.payload
|
||||
init_client_id_ := io.client.release.bits.header.src
|
||||
release_data_needs_write := co.messageHasData(io.client.release.bits.payload)
|
||||
io.client.release.meta.ready := Bool(true)
|
||||
when( io.client.release.meta.valid ) {
|
||||
xact := io.client.release.meta.bits.payload
|
||||
init_client_id_ := io.client.release.meta.bits.header.src
|
||||
release_data_needs_write := co.messageHasData(io.client.release.meta.bits.payload)
|
||||
mem_cnt := UFix(0)
|
||||
mem_cmd_sent := Bool(false)
|
||||
state := s_mem
|
||||
|
|
@ -153,10 +151,9 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: Uncore
|
|||
}
|
||||
is(s_mem) {
|
||||
when (release_data_needs_write) {
|
||||
doOuterReqWrite(io.master.acquire,
|
||||
io.master.acquire_data,
|
||||
io.client.release_data,
|
||||
release_data_needs_write,
|
||||
doOuterReqWrite(io.master.acquire,
|
||||
io.client.release.data,
|
||||
release_data_needs_write,
|
||||
mem_cmd_sent,
|
||||
init_client_id_)
|
||||
} . otherwise { state := s_ack }
|
||||
|
|
@ -192,20 +189,20 @@ class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfigura
|
|||
if (conf.ln.nClients > 1) {
|
||||
// issue self-probes for uncached read xacts to facilitate I$ coherence
|
||||
val probe_self = Bool(true) //co.needsSelfProbe(io.client.acquire.bits.payload)
|
||||
val myflag = Mux(probe_self, Bits(0), UFixToOH(io.client.acquire.bits.header.src(log2Up(conf.ln.nClients)-1,0)))
|
||||
val myflag = Mux(probe_self, Bits(0), UFixToOH(io.client.acquire.meta.bits.header.src(log2Up(conf.ln.nClients)-1,0)))
|
||||
probe_initial_flags := ~(io.tile_incoherent | myflag)
|
||||
}
|
||||
|
||||
io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, io.client.acquire.bits.payload.addr) && (state != s_idle)
|
||||
io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.bits.payload.addr) && (state != s_idle)
|
||||
io.master.acquire.valid := Bool(false)
|
||||
io.master.acquire.bits.payload := co.getUncachedReadAcquire(xact.addr, UFix(trackerId))
|
||||
io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, io.client.acquire.meta.bits.payload.addr) && (state != s_idle)
|
||||
io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.meta.bits.payload.addr) && (state != s_idle)
|
||||
io.master.acquire.meta.valid := Bool(false)
|
||||
io.master.acquire.meta.bits.payload := co.getUncachedReadAcquire(xact.addr, UFix(trackerId))
|
||||
//TODO io.master.acquire.bits.header.dst
|
||||
io.master.acquire.bits.header.src := UFix(bankId)
|
||||
io.master.acquire_data.valid := Bool(false)
|
||||
io.master.acquire_data.bits.payload.data := UFix(0)
|
||||
io.master.acquire.meta.bits.header.src := UFix(bankId)
|
||||
io.master.acquire.data.valid := Bool(false)
|
||||
io.master.acquire.data.bits.payload.data := UFix(0)
|
||||
//TODO io.master.acquire_data.bits.header.dst
|
||||
io.master.acquire_data.bits.header := UFix(bankId)
|
||||
io.master.acquire.data.bits.header := UFix(bankId)
|
||||
io.client.probe.valid := Bool(false)
|
||||
io.client.probe.bits.payload.p_type := co.getProbeType(xact.a_type, UFix(0))
|
||||
io.client.probe.bits.payload.master_xact_id := UFix(trackerId)
|
||||
|
|
@ -219,22 +216,22 @@ class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfigura
|
|||
io.client.grant.bits.header.dst := init_client_id_
|
||||
io.client.grant.bits.header.src := UFix(bankId)
|
||||
io.client.grant.valid := (io.master.grant.valid && (UFix(trackerId) === io.master.grant.bits.payload.client_xact_id))
|
||||
io.client.acquire.ready := Bool(false)
|
||||
io.client.acquire_data.ready := Bool(false)
|
||||
io.client.release.ready := Bool(false)
|
||||
io.client.release_data.ready := Bool(false)
|
||||
io.client.acquire.meta.ready := Bool(false)
|
||||
io.client.acquire.data.ready := Bool(false)
|
||||
io.client.release.meta.ready := Bool(false)
|
||||
io.client.release.data.ready := Bool(false)
|
||||
io.master.grant.ready := io.client.grant.ready
|
||||
io.client.grant_ack.valid := Bool(false)
|
||||
|
||||
switch (state) {
|
||||
is(s_idle) {
|
||||
io.client.acquire.ready := Bool(true)
|
||||
when( io.client.acquire.valid ) {
|
||||
xact := io.client.acquire.bits.payload
|
||||
init_client_id_ := io.client.acquire.bits.header.src
|
||||
io.client.acquire.meta.ready := Bool(true)
|
||||
when( io.client.acquire.meta.valid ) {
|
||||
xact := io.client.acquire.meta.bits.payload
|
||||
init_client_id_ := io.client.acquire.meta.bits.header.src
|
||||
init_sharer_cnt_ := UFix(conf.ln.nClients) // TODO: Broadcast only
|
||||
acquire_data_needs_write := co.messageHasData(io.client.acquire.bits.payload)
|
||||
x_needs_read := co.needsOuterRead(io.client.acquire.bits.payload.a_type, UFix(0))
|
||||
acquire_data_needs_write := co.messageHasData(io.client.acquire.meta.bits.payload)
|
||||
x_needs_read := co.needsOuterRead(io.client.acquire.meta.bits.payload.a_type, UFix(0))
|
||||
probe_flags := probe_initial_flags
|
||||
mem_cnt := UFix(0)
|
||||
r_w_mem_cmd_sent := Bool(false)
|
||||
|
|
@ -253,21 +250,20 @@ class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfigura
|
|||
when(io.client.probe.ready) {
|
||||
probe_flags := probe_flags & ~(UFixToOH(curr_p_id))
|
||||
}
|
||||
io.client.release.ready := Bool(true)
|
||||
when(io.client.release.valid) {
|
||||
io.client.release.meta.ready := Bool(true)
|
||||
when(io.client.release.meta.valid) {
|
||||
if(conf.ln.nClients > 1) release_count := release_count - UFix(1)
|
||||
when(release_count === UFix(1)) {
|
||||
state := s_mem
|
||||
}
|
||||
when( co.messageHasData(io.client.release.bits.payload)) {
|
||||
when( co.messageHasData(io.client.release.meta.bits.payload)) {
|
||||
release_data_needs_write := Bool(true)
|
||||
release_data_client_id := io.client.release.bits.header.src
|
||||
release_data_client_id := io.client.release.meta.bits.header.src
|
||||
}
|
||||
}
|
||||
when (release_data_needs_write) {
|
||||
doOuterReqWrite(io.master.acquire,
|
||||
io.master.acquire_data,
|
||||
io.client.release_data,
|
||||
doOuterReqWrite(io.master.acquire,
|
||||
io.client.release.data,
|
||||
release_data_needs_write,
|
||||
r_w_mem_cmd_sent,
|
||||
release_data_client_id)
|
||||
|
|
@ -275,18 +271,16 @@ class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfigura
|
|||
}
|
||||
is(s_mem) {
|
||||
when (release_data_needs_write) {
|
||||
doOuterReqWrite(io.master.acquire,
|
||||
io.master.acquire_data,
|
||||
io.client.release_data,
|
||||
release_data_needs_write,
|
||||
r_w_mem_cmd_sent,
|
||||
doOuterReqWrite(io.master.acquire,
|
||||
io.client.release.data,
|
||||
release_data_needs_write,
|
||||
r_w_mem_cmd_sent,
|
||||
release_data_client_id)
|
||||
} . elsewhen(acquire_data_needs_write) {
|
||||
doOuterReqWrite(io.master.acquire,
|
||||
io.master.acquire_data,
|
||||
io.client.acquire_data,
|
||||
acquire_data_needs_write,
|
||||
a_w_mem_cmd_sent,
|
||||
doOuterReqWrite(io.master.acquire,
|
||||
io.client.acquire.data,
|
||||
acquire_data_needs_write,
|
||||
a_w_mem_cmd_sent,
|
||||
init_client_id_)
|
||||
} . elsewhen (x_needs_read) {
|
||||
doOuterReqRead(io.master.acquire, x_needs_read)
|
||||
|
|
@ -313,18 +307,18 @@ abstract trait OuterRequestGenerator {
|
|||
val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
|
||||
val mem_cnt_next = mem_cnt + UFix(1)
|
||||
|
||||
def doOuterReqWrite[T <: Data](master_acq: FIFOIO[LogicalNetworkIO[Acquire]], master_acq_data: FIFOIO[LogicalNetworkIO[AcquireData]], client_data: FIFOIO[LogicalNetworkIO[T]], trigger: Bool, cmd_sent: Bool, desired_client_data_src_id: UFix) {
|
||||
def doOuterReqWrite[T <: HasMemData](master_acq: PairedDataIO[LogicalNetworkIO[Acquire],LogicalNetworkIO[AcquireData]], client_data: FIFOIO[LogicalNetworkIO[T]], trigger: Bool, cmd_sent: Bool, desired_client_data_src_id: UFix) {
|
||||
val do_write = client_data.valid && (client_data.bits.header.src === desired_client_data_src_id)
|
||||
master_acq.bits.payload := cmd_to_write
|
||||
master_acq_data.bits.payload := client_data.bits.payload
|
||||
when(master_acq.ready && master_acq.valid) {
|
||||
master_acq.meta.bits.payload := cmd_to_write
|
||||
master_acq.data.bits.payload := client_data.bits.payload
|
||||
when(master_acq.meta.fire()) {
|
||||
cmd_sent := Bool(true)
|
||||
}
|
||||
when (do_write) {
|
||||
master_acq.valid := !cmd_sent && master_acq_data.ready
|
||||
when (master_acq.ready || cmd_sent) {
|
||||
master_acq_data.valid := client_data.valid
|
||||
when(master_acq_data.ready) {
|
||||
master_acq.meta.valid := !cmd_sent
|
||||
when (master_acq.meta.ready || cmd_sent) {
|
||||
master_acq.data.valid := client_data.valid
|
||||
when(master_acq.data.ready) {
|
||||
client_data.ready:= Bool(true)
|
||||
mem_cnt := mem_cnt_next
|
||||
when(mem_cnt === UFix(REFILL_CYCLES-1)) {
|
||||
|
|
@ -335,10 +329,10 @@ abstract trait OuterRequestGenerator {
|
|||
}
|
||||
}
|
||||
|
||||
def doOuterReqRead(master_acq: FIFOIO[LogicalNetworkIO[Acquire]], trigger: Bool) {
|
||||
master_acq.valid := Bool(true)
|
||||
master_acq.bits.payload := cmd_to_read
|
||||
when(master_acq.ready) {
|
||||
def doOuterReqRead(master_acq: PairedDataIO[LogicalNetworkIO[Acquire],LogicalNetworkIO[AcquireData]], trigger: Bool) {
|
||||
master_acq.meta.valid := Bool(true)
|
||||
master_acq.meta.bits.payload := cmd_to_read
|
||||
when(master_acq.meta.ready) {
|
||||
trigger := Bool(false)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user