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use new locking round robin arbiter

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This commit is contained in:
Henry Cook 2013-04-22 16:48:55 -07:00
parent fedc2753e4
commit 9a258e7fb4
1 changed files with 2 additions and 49 deletions
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51
uncore/src/package.scala
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@ -6,6 +6,8 @@ import scala.collection.mutable.Stack
//TODO: Remove these Networking classes from the package object once Scala bug
//SI-3439 is resolved.
implicit def toOption[A](a: A) = Option(a)
case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
@ -24,55 +26,6 @@ class BasicCrossbarIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkCon
abstract class PhysicalNetwork(conf: PhysicalNetworkConfiguration) extends Component
class LockingRRArbiter[T <: Data](n: Int, count: Int)(data: => T) extends Component {
val io = new ioArbiter(n)(data)
val cnt = Reg(resetVal = UFix(0, width = log2Up(count)))
val cnt_next = cnt + UFix(1)
val locked = Reg(resetVal = Bool(false))
val lock_idx = Reg(resetVal = UFix(n))
if(count > 1){
when(io.out.valid && io.out.ready) {
cnt := cnt_next
when(!locked) {
locked := Bool(true)
lock_idx := Vec(io.in.map{ in => in.ready && in.valid}){Bool()}.indexWhere{i: Bool => i}
}
when(cnt_next === UFix(0)) {
locked := Bool(false)
}
}
} else {
locked := Bool(false)
lock_idx := UFix(n)
cnt := UFix(0)
}
val last_grant = Reg(resetVal = Bits(0, log2Up(n)))
val g = ArbiterCtrl((0 until n).map(i => io.in(i).valid && UFix(i) > last_grant) ++ io.in.map(_.valid))
val grant = (0 until n).map(i => g(i) && UFix(i) > last_grant || g(i+n))
(0 until n).map(i => io.in(i).ready := Mux(locked, lock_idx === UFix(i), grant(i)) && io.out.ready)
var choose = Bits(n-1)
for (i <- n-2 to 0 by -1)
choose = Mux(io.in(i).valid, Bits(i), choose)
for (i <- n-1 to 1 by -1)
choose = Mux(io.in(i).valid && UFix(i) > last_grant, Bits(i), choose)
choose = Mux(locked, lock_idx, choose)
when (io.out.valid && io.out.ready) {
last_grant := choose
}
val dvec = Vec(n) { data }
(0 until n).map(i => dvec(i) := io.in(i).bits )
io.out.valid := Mux(locked, io.in(lock_idx).valid, io.in.map(_.valid).foldLeft(Bool(false))( _ || _))
io.out.bits := dvec(choose)
io.chosen := choose
}
class BasicCrossbar[T <: Data](count: Int)(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
val io = new Bundle {
val in = Vec(conf.nEndpoints){(new FIFOIO){(new BasicCrossbarIO){data}}}.flip