Merge branch 'master' of github.com:ucb-bar/reference-chip
This commit is contained in:
2
chisel
2
chisel
Submodule chisel updated: 11cb15ba9a...2c93b2d07d
Submodule riscv-rocket updated: 00a230c369...9ace637d7b
@ -298,7 +298,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
|
||||
|
||||
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
|
||||
if(lnWithHtifConf.nMasters > 1) {
|
||||
val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
|
||||
val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
|
||||
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
|
||||
conv.io.uncached <> arb.io.out
|
||||
} else {
|
||||
|
@ -31,7 +31,7 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
|
||||
|
||||
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
|
||||
if(lnWithHtifConf.nMasters > 1) {
|
||||
val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
|
||||
val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
|
||||
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
|
||||
conv.io.uncached <> arb.io.out
|
||||
} else {
|
||||
|
2
uncore
2
uncore
Submodule uncore updated: f238f04fd9...cd75291f29
Reference in New Issue
Block a user