initial attempt at upgrade
This commit is contained in:
Henry Cook
parent
199e76fc77
commit
11e131af47
2
chisel
2
chisel
@ -1 +1 @@
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Subproject commit 11cb15ba9a0f7dedf43a34e0d64708facd0ea619
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Subproject commit 97ac878580bdd9bf9d4cf05d33d64689dfc6627a
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@ -1 +1 @@
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Subproject commit fc09bea89982c4d7d33b6201896aa3b40caba186
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Subproject commit 76ac1cb932949dc33a11dd85f9bf9cbc3a639eb4
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@ -1 +1 @@
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Subproject commit ee815dd3983f3b1a67fd3d810a513e23bdef97e4
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Subproject commit 2d3caa3e269f238b1a8ccaa28f0c348dc12acf61
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@ -9,19 +9,20 @@ import scala.collection.mutable.ArrayBuffer
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import scala.collection.mutable.HashMap
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object DummyTopLevelConstants {
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val NTILES = 2
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val NTILES = 1
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val NBANKS = 1
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val HTIF_WIDTH = 16
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val ENABLE_SHARING = true
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val ENABLE_CLEAN_EXCLUSIVE = true
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val HAS_VEC = true
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val HAS_FPU = true
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val NL2_REL_XACTS = 1
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val NL2_ACQ_XACTS = 8
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val NMSHRS = 2
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}
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object ReferenceChipBackend {
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val initMap = new HashMap[Component, Bool]()
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val initMap = new HashMap[Module, Bool]()
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}
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class ReferenceChipBackend extends VerilogBackend
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@ -35,15 +36,15 @@ class ReferenceChipBackend extends VerilogBackend
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(if (idx == 0) res.toString else "") + super.emitPortDef(m, idx)
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}
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def addMemPin(c: Component) = {
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for (node <- Component.nodes) {
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def addMemPin(c: Module) = {
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for (node <- Module.nodes) {
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if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) {
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connectMemPin(c, node.component, node)
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}
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}
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}
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def connectMemPin(topC: Component, c: Component, p: Node): Unit = {
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def connectMemPin(topC: Module, c: Module, p: Node): Unit = {
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var isNewPin = false
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val compInitPin =
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if (initMap.contains(c)) {
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@ -64,7 +65,7 @@ class ReferenceChipBackend extends VerilogBackend
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}
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}
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def addTopLevelPin(c: Component) = {
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def addTopLevelPin(c: Module) = {
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val init = Bool(INPUT)
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init.setName("init")
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init.component = c
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@ -72,37 +73,37 @@ class ReferenceChipBackend extends VerilogBackend
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initMap += (c -> init)
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}
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transforms += ((c: Component) => addTopLevelPin(c))
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transforms += ((c: Component) => addMemPin(c))
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transforms += ((c: Module) => addTopLevelPin(c))
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transforms += ((c: Module) => addMemPin(c))
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}
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class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component
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class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
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{
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implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2)
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val io = new Bundle {
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val tiles = Vec(conf.nTiles) { new TileLinkIO }.flip
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val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
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val htif = (new TileLinkIO).flip
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val incoherent = Vec(ln.nClients) { Bool() }.asInput
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val incoherent = Vec.fill(ln.nClients){Bool()}.asInput
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val mem = new ioMem
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val mem_backup = new ioMemSerialized(htif_width)
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val mem_backup_en = Bool(INPUT)
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}
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val llc_tag_leaf = Mem(512, seqRead = true) { Bits(width = 152) }
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val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
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//val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
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val llc = new DRAMSideLLCNull(8, REFILL_CYCLES)
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val mem_serdes = new MemSerdes(htif_width)
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val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true)
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val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true)
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val llc = Module(new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf))
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//val llc = Module(new DRAMSideLLCNull(8, REFILL_CYCLES))
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val mem_serdes = Module(new MemSerdes(htif_width))
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require(clientEndpoints.length == ln.nClients)
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val masterEndpoints = (0 until ln.nMasters).map(new L2CoherenceAgent(_))
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val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)
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val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
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val net = Module(new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints))
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net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
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masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
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val conv = new MemIOUncachedTileLinkIOConverter(2)
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val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
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if(ln.nMasters > 1) {
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val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters)
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val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters))
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arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
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conv.io.uncached <> arb.io.out
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} else {
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@ -113,7 +114,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
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conv.io.mem.resp <> llc.io.cpu.resp
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// mux between main and backup memory ports
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val mem_cmdq = (new Queue(2)) { new MemReqCmd }
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val mem_cmdq = Module(new Queue(new MemReqCmd, 2))
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mem_cmdq.io.enq <> llc.io.mem.req_cmd
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mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
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io.mem.req_cmd.valid := mem_cmdq.io.deq.valid && !io.mem_backup_en
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@ -121,7 +122,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
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mem_serdes.io.wide.req_cmd.valid := mem_cmdq.io.deq.valid && io.mem_backup_en
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mem_serdes.io.wide.req_cmd.bits := mem_cmdq.io.deq.bits
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val mem_dataq = (new Queue(REFILL_CYCLES)) { new MemData }
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val mem_dataq = Module(new Queue(new MemData, REFILL_CYCLES))
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mem_dataq.io.enq <> llc.io.mem.req_data
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mem_dataq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_data.ready, io.mem.req_data.ready)
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io.mem.req_data.valid := mem_dataq.io.deq.valid && !io.mem_backup_en
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@ -138,21 +139,21 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
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case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int)
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class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component
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class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
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{
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implicit val tl = conf.tl
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val io = new Bundle {
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val debug = new DebugIO()
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val host = new HostIO(htif_width)
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val mem = new ioMem
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val tiles = Vec(conf.nTiles) { new TileLinkIO }.flip
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val htif = Vec(conf.nTiles) { new HTIFIO(conf.nTiles) }.flip
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val incoherent = Vec(conf.nTiles) { Bool() }.asInput
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val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
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val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
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val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
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val mem_backup = new ioMemSerialized(htif_width)
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val mem_backup_en = Bool(INPUT)
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}
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val htif = new RocketHTIF(htif_width)
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val outmemsys = new OuterMemorySystem(htif_width, tileList :+ htif)
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val htif = Module(new RocketHTIF(htif_width))
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val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif))
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val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
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outmemsys.io.incoherent := incoherentWithHtif
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htif.io.cpu <> io.htif
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@ -160,7 +161,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
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outmemsys.io.mem_backup_en <> io.mem_backup_en
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// Add networking headers and endpoint queues
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def convertAddrToBank(addr: Bits): UFix = {
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def convertAddrToBank(addr: Bits): UInt = {
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require(conf.bankIdLsb + log2Up(conf.nBanks) < MEM_ADDR_BITS, {println("Invalid bits for bank multiplexing.")})
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addr(conf.bankIdLsb + log2Up(conf.nBanks) - 1, conf.bankIdLsb)
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}
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@ -173,7 +174,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
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val grant_ack_q = Queue(client.grant_ack)
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outer.grant_ack.valid := grant_ack_q.valid
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outer.grant_ack.bits := grant_ack_q.bits
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outer.grant_ack.bits.header.src := UFix(i)
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outer.grant_ack.bits.header.src := UInt(i)
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grant_ack_q.ready := outer.grant_ack.ready
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client.grant <> Queue(outer.grant, 1, pipe = true)
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@ -181,7 +182,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
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}
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// pad out the HTIF using a divided clock
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val hio = (new SlowIO(512)) { Bits(width = htif_width+1) }
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val hio = Module((new SlowIO(512)) { Bits(width = htif_width+1) })
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hio.io.set_divisor.valid := htif.io.scr.wen && htif.io.scr.waddr === 63
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hio.io.set_divisor.bits := htif.io.scr.wdata
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htif.io.scr.rdata(63) := hio.io.divisor
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@ -205,7 +206,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
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htif.io.host.in.bits := hio.io.in_fast.bits
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hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready)
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io.host.clk := hio.io.clk_slow
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io.host.clk_edge := Reg(io.host.clk && !Reg(io.host.clk))
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io.host.clk_edge := RegUpdate(io.host.clk && !RegUpdate(io.host.clk))
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}
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class TopIO(htifWidth: Int) extends Bundle {
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@ -224,14 +225,14 @@ class VLSITopIO(htifWidth: Int) extends TopIO(htifWidth) {
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import DummyTopLevelConstants._
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class MemDessert extends Component {
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class MemDessert extends Module {
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val io = new MemDesserIO(HTIF_WIDTH)
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val x = new MemDesser(HTIF_WIDTH)
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val x = Module(new MemDesser(HTIF_WIDTH))
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io.narrow <> x.io.narrow
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io.wide <> x.io.wide
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}
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class Top extends Component {
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class Top extends Module {
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val co = if(ENABLE_SHARING) {
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if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence
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else new MSICoherence
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@ -249,13 +250,13 @@ class Top extends Component {
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val dc = DCacheConfig(128, 4, ntlb = 8,
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nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
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val rc = RocketConfiguration(tl, ic, dc,
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fpu = true, vec = HAS_VEC)
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fpu = HAS_FPU, vec = HAS_VEC)
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val io = new VLSITopIO(HTIF_WIDTH)
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val resetSigs = Vec(uc.nTiles){Bool()}
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val tileList = (0 until uc.nTiles).map(r => new Tile(resetSignal = resetSigs(r))(rc))
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val uncore = new Uncore(HTIF_WIDTH, tileList)
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val resetSigs = Vec.fill(uc.nTiles){Bool()}
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val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
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val uncore = Module(new Uncore(HTIF_WIDTH, tileList))
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var error_mode = Bool(false)
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for (i <- 0 until uc.nTiles) {
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@ -267,12 +268,12 @@ class Top extends Component {
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val tile = tileList(i)
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tile.io.tilelink <> tl
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il := hl.reset
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tile.io.host.reset := Reg(Reg(hl.reset))
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tile.io.host.reset := RegUpdate(RegUpdate(hl.reset))
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tile.io.host.pcr_req <> Queue(hl.pcr_req)
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hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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error_mode = error_mode || Reg(tile.io.host.debug.error_mode)
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error_mode = error_mode || RegUpdate(tile.io.host.debug.error_mode)
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}
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io.host <> uncore.io.host
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@ -5,26 +5,26 @@ import Node._
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import uncore._
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import rocket._
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class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component
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class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
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{
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implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2)
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val io = new Bundle {
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val tiles = Vec(conf.nTiles) { new TileLinkIO }.flip
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val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
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val htif = (new TileLinkIO).flip
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val incoherent = Vec(ln.nClients) { Bool() }.asInput
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val incoherent = Vec.fill(ln.nClients){Bool()}.asInput
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val mem = new ioMem
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}
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require(clientEndpoints.length == ln.nClients)
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val masterEndpoints = (0 until ln.nMasters).map(new L2CoherenceAgent(_))
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val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
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val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)
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val net = Module(new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints))
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net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
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masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
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val conv = new MemIOUncachedTileLinkIOConverter(2)
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val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
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if(ln.nMasters > 1) {
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val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters)
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val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters))
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arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
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conv.io.uncached <> arb.io.out
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} else {
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@ -35,24 +35,24 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
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conv.io.mem.resp <> Queue(io.mem.resp)
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}
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class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component
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class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
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{
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implicit val (tl, ln) = (conf.tl, conf.tl.ln)
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val io = new Bundle {
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val debug = new DebugIO()
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val host = new HostIO(htif_width)
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val mem = new ioMem
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val tiles = Vec(conf.nTiles) { new TileLinkIO }.flip
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val htif = Vec(conf.nTiles) { new HTIFIO(conf.nTiles) }.flip
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val incoherent = Vec(conf.nTiles) { Bool() }.asInput
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val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
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val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
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val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
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}
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val htif = new RocketHTIF(htif_width)
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val outmemsys = new FPGAOuterMemorySystem(htif_width, tileList :+ htif)
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val htif = Module(new RocketHTIF(htif_width))
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val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif))
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htif.io.cpu <> io.htif
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outmemsys.io.mem <> io.mem
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// Add networking headers and endpoint queues
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def convertAddrToBank(addr: Bits): UFix = {
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def convertAddrToBank(addr: Bits): UInt = {
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require(conf.bankIdLsb + log2Up(conf.nBanks) < MEM_ADDR_BITS, {println("Invalid bits for bank multiplexing.")})
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addr(conf.bankIdLsb + log2Up(conf.nBanks) - 1, conf.bankIdLsb)
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}
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@ -66,7 +66,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
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val grant_ack_q = Queue(client.grant_ack)
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outer.grant_ack.valid := grant_ack_q.valid
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outer.grant_ack.bits := grant_ack_q.bits
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outer.grant_ack.bits.header.src := UFix(i)
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outer.grant_ack.bits.header.src := UInt(i)
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grant_ack_q.ready := outer.grant_ack.ready
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client.grant <> Queue(outer.grant, 1, pipe = true)
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@ -79,7 +79,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
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class FPGATopIO(htifWidth: Int) extends TopIO(htifWidth)
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class FPGATop extends Component {
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class FPGATop extends Module {
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val htif_width = 16
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val co = new MESICoherence
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val ntiles = 1
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@ -98,9 +98,9 @@ class FPGATop extends Component {
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val io = new FPGATopIO(htif_width)
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val resetSigs = Vec(uc.nTiles){Bool()}
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val tileList = (0 until uc.nTiles).map(r => new Tile(resetSignal = resetSigs(r))(rc))
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val uncore = new FPGAUncore(htif_width, tileList)
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val resetSigs = Vec.fill(uc.nTiles){Bool()}
|
||||
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
|
||||
val uncore = Module(new FPGAUncore(htif_width, tileList))
|
||||
|
||||
io.debug.error_mode := Bool(false)
|
||||
for (i <- 0 until uc.nTiles) {
|
||||
@ -113,7 +113,7 @@ class FPGATop extends Component {
|
||||
|
||||
tile.io.tilelink <> tl
|
||||
il := hl.reset
|
||||
tile.io.host.reset := Reg(Reg(hl.reset))
|
||||
tile.io.host.reset := RegUpdate(RegUpdate(hl.reset))
|
||||
tile.io.host.pcr_req <> Queue(hl.pcr_req)
|
||||
hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
|
||||
hl.ipi_req <> Queue(tile.io.host.ipi_req)
|
||||
@ -126,12 +126,12 @@ class FPGATop extends Component {
|
||||
io.mem <> uncore.io.mem
|
||||
}
|
||||
|
||||
abstract class AXISlave extends Component {
|
||||
abstract class AXISlave extends Module {
|
||||
val aw = 5
|
||||
val dw = 32
|
||||
val io = new Bundle {
|
||||
val in = new FIFOIO()(Bits(width = dw)).flip
|
||||
val out = new FIFOIO()(Bits(width = dw))
|
||||
val in = Decoupled(Bits(width = dw)).flip
|
||||
val out = Decoupled(Bits(width = dw))
|
||||
val addr = Bits(INPUT, aw)
|
||||
}
|
||||
}
|
||||
@ -144,11 +144,11 @@ class Slave extends AXISlave
|
||||
val htifw = top.io.host.in.bits.getWidth
|
||||
|
||||
val n = 4 // htif, mem req/read data, mem write data, error mode
|
||||
def wen(i: Int) = io.in.valid && io.addr(log2Up(n)-1,0) === UFix(i)
|
||||
def ren(i: Int) = io.out.ready && io.addr(log2Up(n)-1,0) === UFix(i)
|
||||
val rdata = Vec(n){Bits(width = dw)}
|
||||
val rvalid = Vec(n){Bool()}
|
||||
val wready = Vec(n){Bool()}
|
||||
def wen(i: Int) = io.in.valid && io.addr(log2Up(n)-1,0) === UInt(i)
|
||||
def ren(i: Int) = io.out.ready && io.addr(log2Up(n)-1,0) === UInt(i)
|
||||
val rdata = Vec.fill(n){Bits(width = dw)}
|
||||
val rvalid = Vec.fill(n){Bool()}
|
||||
val wready = Vec.fill(n){Bool()}
|
||||
|
||||
io.in.ready := wready(io.addr)
|
||||
io.out.valid := rvalid(io.addr)
|
||||
@ -167,7 +167,7 @@ class Slave extends AXISlave
|
||||
|
||||
// read cr1 -> mem.req_cmd (nonblocking)
|
||||
// the memory system is FIFO from hereon out, so just remember the tags here
|
||||
val tagq = new Queue(4)(top.io.mem.req_cmd.bits.tag.clone)
|
||||
val tagq = Module(new Queue(top.io.mem.req_cmd.bits.tag, 4))
|
||||
tagq.io.enq.bits := top.io.mem.req_cmd.bits.tag
|
||||
tagq.io.enq.valid := ren(1) && top.io.mem.req_cmd.valid && !top.io.mem.req_cmd.bits.rw
|
||||
top.io.mem.req_cmd.ready := ren(1)
|
||||
@ -176,29 +176,29 @@ class Slave extends AXISlave
|
||||
require(dw >= top.io.mem.req_cmd.bits.addr.getWidth + 1 + 1)
|
||||
|
||||
// write cr1 -> mem.resp (nonblocking)
|
||||
val in_count = Reg(resetVal = UFix(0, log2Up(memw/dw)))
|
||||
val rf_count = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
|
||||
val in_count = RegReset(UInt(0, log2Up(memw/dw)))
|
||||
val rf_count = RegReset(UInt(0, log2Up(REFILL_CYCLES)))
|
||||
require(memw % dw == 0 && isPow2(memw/dw))
|
||||
val in_reg = Reg{top.io.mem.resp.bits.data.clone}
|
||||
val in_reg = Reg(top.io.mem.resp.bits.data)
|
||||
top.io.mem.resp.bits.data := Cat(io.in.bits, in_reg(in_reg.getWidth-1,dw))
|
||||
top.io.mem.resp.bits.tag := tagq.io.deq.bits
|
||||
top.io.mem.resp.valid := wen(1) && in_count.andR
|
||||
tagq.io.deq.ready := top.io.mem.resp.fire() && rf_count.andR
|
||||
wready(1) := top.io.mem.resp.ready
|
||||
when (wen(1) && wready(1)) {
|
||||
in_count := in_count + UFix(1)
|
||||
in_count := in_count + UInt(1)
|
||||
in_reg := top.io.mem.resp.bits.data
|
||||
}
|
||||
when (top.io.mem.resp.fire()) {
|
||||
rf_count := rf_count + UFix(1)
|
||||
rf_count := rf_count + UInt(1)
|
||||
}
|
||||
|
||||
// read cr2 -> mem.req_data (blocking)
|
||||
val out_count = Reg(resetVal = UFix(0, log2Up(memw/dw)))
|
||||
val out_count = RegReset(UInt(0, log2Up(memw/dw)))
|
||||
top.io.mem.req_data.ready := ren(2) && out_count.andR
|
||||
rdata(2) := top.io.mem.req_data.bits.data >> (out_count * UFix(dw))
|
||||
rdata(2) := top.io.mem.req_data.bits.data >> (out_count * UInt(dw))
|
||||
rvalid(2) := top.io.mem.req_data.valid
|
||||
when (ren(2) && rvalid(2)) { out_count := out_count + UFix(1) }
|
||||
when (ren(2) && rvalid(2)) { out_count := out_count + UInt(1) }
|
||||
|
||||
// read cr3 -> error mode (nonblocking)
|
||||
rdata(3) := Cat(top.io.mem.req_cmd.valid, tagq.io.enq.ready, top.io.debug.error_mode)
|
||||
|
||||
@ -5,19 +5,19 @@ import uncore._
|
||||
import scala.reflect._
|
||||
|
||||
object TileLinkHeaderAppender {
|
||||
def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](in: ClientSourcedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(implicit conf: TileLinkConfiguration) = {
|
||||
val shim = new TileLinkHeaderAppender(clientId, nBanks, addrConvert)(in.meta.bits.payload.clone, in.data.bits.payload.clone)
|
||||
def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](in: ClientSourcedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
|
||||
val shim = Module(new TileLinkHeaderAppender(clientId, nBanks, addrConvert)(in.meta.bits.payload.clone, in.data.bits.payload.clone))
|
||||
shim.io.in <> in
|
||||
shim.io.out
|
||||
}
|
||||
def apply[T <: SourcedMessage with HasPhysicalAddress](in: ClientSourcedFIFOIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(implicit conf: TileLinkConfiguration) = {
|
||||
val shim = new TileLinkHeaderAppender(clientId, nBanks, addrConvert)(in.bits.payload.clone, new AcquireData)
|
||||
def apply[T <: SourcedMessage with HasPhysicalAddress](in: ClientSourcedFIFOIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
|
||||
val shim = Module(new TileLinkHeaderAppender(clientId, nBanks, addrConvert)(in.bits.payload.clone, new AcquireData))
|
||||
shim.io.in.meta <> in
|
||||
shim.io.out.meta
|
||||
}
|
||||
}
|
||||
|
||||
class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(metadata: => T, data: => U)(implicit conf: TileLinkConfiguration) extends Component {
|
||||
class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(metadata: => T, data: => U)(implicit conf: TileLinkConfiguration) extends Module {
|
||||
implicit val ln = conf.ln
|
||||
val io = new Bundle {
|
||||
val in = new ClientSourcedDataIO()((new LogicalNetworkIO){ metadata }, (new LogicalNetworkIO){ data }).flip
|
||||
@ -28,26 +28,26 @@ class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: S
|
||||
val data_q = Queue(io.in.data)
|
||||
if(nBanks == 1) {
|
||||
io.out.meta.bits.payload := meta_q.bits.payload
|
||||
io.out.meta.bits.header.src := UFix(clientId)
|
||||
io.out.meta.bits.header.dst := UFix(0)
|
||||
io.out.meta.bits.header.src := UInt(clientId)
|
||||
io.out.meta.bits.header.dst := UInt(0)
|
||||
io.out.meta.valid := meta_q.valid
|
||||
meta_q.ready := io.out.meta.ready
|
||||
io.out.data.bits.payload := data_q.bits.payload
|
||||
io.out.data.bits.header.src := UFix(clientId)
|
||||
io.out.data.bits.header.dst := UFix(0)
|
||||
io.out.data.bits.header.src := UInt(clientId)
|
||||
io.out.data.bits.header.dst := UInt(0)
|
||||
io.out.data.valid := data_q.valid
|
||||
data_q.ready := io.out.data.ready
|
||||
} else {
|
||||
val meta_has_data = conf.co.messageHasData(meta_q.bits.payload)
|
||||
val addr_q = (new Queue(2, pipe = true, flow = true)){io.in.meta.bits.payload.addr.clone}
|
||||
val data_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
|
||||
val data_cnt_up = data_cnt + UFix(1)
|
||||
val addr_q = Module(new Queue(io.in.meta.bits.payload.addr.clone, 2, pipe = true, flow = true))
|
||||
val data_cnt = RegReset(UInt(0, width = log2Up(REFILL_CYCLES)))
|
||||
val data_cnt_up = data_cnt + UInt(1)
|
||||
|
||||
io.out.meta.bits.payload := meta_q.bits.payload
|
||||
io.out.meta.bits.header.src := UFix(clientId)
|
||||
io.out.meta.bits.header.src := UInt(clientId)
|
||||
io.out.meta.bits.header.dst := addrConvert(meta_q.bits.payload.addr)
|
||||
io.out.data.bits.payload := meta_q.bits.payload
|
||||
io.out.data.bits.header.src := UFix(clientId)
|
||||
io.out.data.bits.header.src := UInt(clientId)
|
||||
io.out.data.bits.header.dst := addrConvert(addr_q.io.deq.bits)
|
||||
addr_q.io.enq.bits := meta_q.bits.payload.addr
|
||||
|
||||
@ -60,7 +60,7 @@ class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: S
|
||||
|
||||
when(data_q.valid && data_q.ready) {
|
||||
data_cnt := data_cnt_up
|
||||
when(data_cnt_up === UFix(0)) {
|
||||
when(data_cnt_up === UInt(0)) {
|
||||
addr_q.io.deq.ready := Bool(true)
|
||||
}
|
||||
}
|
||||
@ -68,16 +68,16 @@ class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: S
|
||||
}
|
||||
|
||||
//Adapter betweewn an UncachedTileLinkIO and a mem controller MemIO
|
||||
class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: TileLinkConfiguration) extends Component {
|
||||
class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: TileLinkConfiguration) extends Module {
|
||||
val io = new Bundle {
|
||||
val uncached = new UncachedTileLinkIO().flip
|
||||
val mem = new ioMem
|
||||
}
|
||||
val mem_cmd_q = (new Queue(qDepth)){new MemReqCmd}
|
||||
val mem_data_q = (new Queue(qDepth)){new MemData}
|
||||
val mem_cmd_q = Module(new Queue(new MemReqCmd, qDepth))
|
||||
val mem_data_q = Module(new Queue(new MemData, qDepth))
|
||||
mem_cmd_q.io.enq.valid := io.uncached.acquire.meta.valid
|
||||
io.uncached.acquire.meta.ready := mem_cmd_q.io.enq.ready
|
||||
mem_cmd_q.io.enq.bits.rw := conf.co.needsOuterWrite(io.uncached.acquire.meta.bits.payload.a_type, UFix(0))
|
||||
mem_cmd_q.io.enq.bits.rw := conf.co.needsOuterWrite(io.uncached.acquire.meta.bits.payload.a_type, UInt(0))
|
||||
mem_cmd_q.io.enq.bits.tag := io.uncached.acquire.meta.bits.payload.client_xact_id
|
||||
mem_cmd_q.io.enq.bits.addr := io.uncached.acquire.meta.bits.payload.addr
|
||||
mem_data_q.io.enq.valid := io.uncached.acquire.data.valid
|
||||
@ -87,20 +87,20 @@ class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: TileLinkConfi
|
||||
io.mem.resp.ready := io.uncached.grant.ready
|
||||
io.uncached.grant.bits.payload.data := io.mem.resp.bits.data
|
||||
io.uncached.grant.bits.payload.client_xact_id := io.mem.resp.bits.tag
|
||||
io.uncached.grant.bits.payload.master_xact_id := UFix(0) // DNC
|
||||
io.uncached.grant.bits.payload.g_type := UFix(0) // DNC
|
||||
io.uncached.grant.bits.payload.master_xact_id := UInt(0) // DNC
|
||||
io.uncached.grant.bits.payload.g_type := UInt(0) // DNC
|
||||
io.mem.req_cmd <> mem_cmd_q.io.deq
|
||||
io.mem.req_data <> mem_data_q.io.deq
|
||||
}
|
||||
|
||||
class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf.tl.ln) {
|
||||
implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
|
||||
val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkIO).flip}; case h:MasterCoherenceAgent => {new TileLinkIO}})){ new TileLinkIO }
|
||||
val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkIO).flip}; case h:MasterCoherenceAgent => {new TileLinkIO}}))
|
||||
implicit val pconf = new PhysicalNetworkConfiguration(ln.nEndpoints, ln.idBits) // Same config for all networks
|
||||
|
||||
// Aliases for the various network IO bundle types
|
||||
type FBCIO[T <: Data] = FIFOIO[PhysicalNetworkIO[T]]
|
||||
type FLNIO[T <: Data] = FIFOIO[LogicalNetworkIO[T]]
|
||||
type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
|
||||
type FLNIO[T <: Data] = DecoupledIO[LogicalNetworkIO[T]]
|
||||
type PBCIO[M <: Data, D <: Data] = PairedDataIO[PhysicalNetworkIO[M], PhysicalNetworkIO[D]]
|
||||
type PLNIO[M <: Data, D <: Data] = PairedDataIO[LogicalNetworkIO[M], LogicalNetworkIO[D]]
|
||||
type FromCrossbar[T <: Data] = FBCIO[T] => FLNIO[T]
|
||||
@ -109,7 +109,7 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
|
||||
// Shims for converting between logical network IOs and physical network IOs
|
||||
//TODO: Could be less verbose if you could override subbundles after a <>
|
||||
def DefaultFromCrossbarShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
|
||||
val out = new FIFOIO()(new LogicalNetworkIO()(in.bits.payload.clone)).asDirectionless
|
||||
val out = Decoupled(new LogicalNetworkIO()(in.bits.payload.clone)).asDirectionless
|
||||
out.bits.header := in.bits.header
|
||||
out.bits.payload := in.bits.payload
|
||||
out.valid := in.valid
|
||||
@ -118,16 +118,16 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
|
||||
}
|
||||
def CrossbarToMasterShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
|
||||
val out = DefaultFromCrossbarShim(in)
|
||||
out.bits.header.src := in.bits.header.src - UFix(ln.nMasters)
|
||||
out.bits.header.src := in.bits.header.src - UInt(ln.nMasters)
|
||||
out
|
||||
}
|
||||
def CrossbarToClientShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
|
||||
val out = DefaultFromCrossbarShim(in)
|
||||
out.bits.header.dst := in.bits.header.dst - UFix(ln.nMasters)
|
||||
out.bits.header.dst := in.bits.header.dst - UInt(ln.nMasters)
|
||||
out
|
||||
}
|
||||
def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
|
||||
val out = new FIFOIO()(new PhysicalNetworkIO()(in.bits.payload.clone)).asDirectionless
|
||||
val out = Decoupled(new PhysicalNetworkIO()(in.bits.payload.clone)).asDirectionless
|
||||
out.bits.header := in.bits.header
|
||||
out.bits.payload := in.bits.payload
|
||||
out.valid := in.valid
|
||||
@ -136,12 +136,12 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
|
||||
}
|
||||
def MasterToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
|
||||
val out = DefaultToCrossbarShim(in)
|
||||
out.bits.header.dst := in.bits.header.dst + UFix(ln.nMasters)
|
||||
out.bits.header.dst := in.bits.header.dst + UInt(ln.nMasters)
|
||||
out
|
||||
}
|
||||
def ClientToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
|
||||
val out = DefaultToCrossbarShim(in)
|
||||
out.bits.header.src := in.bits.header.src + UFix(ln.nMasters)
|
||||
out.bits.header.src := in.bits.header.src + UInt(ln.nMasters)
|
||||
out
|
||||
}
|
||||
|
||||
@ -203,20 +203,20 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
|
||||
|
||||
// Actually instantiate the particular networks required for TileLink
|
||||
def acqHasData(acq: PhysicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
|
||||
val acq_net = new PairedCrossbar(REFILL_CYCLES, acqHasData _)(new Acquire, new AcquireData)
|
||||
val acq_net = Module(new PairedCrossbar(REFILL_CYCLES, acqHasData _)(new Acquire, new AcquireData))
|
||||
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, acq_net.io.in(id), acq_net.io.out(id), io.acquire) }
|
||||
|
||||
def relHasData(rel: PhysicalNetworkIO[Release]) = co.messageHasData(rel.payload)
|
||||
val rel_net = new PairedCrossbar(REFILL_CYCLES, relHasData _)(new Release, new ReleaseData)
|
||||
val rel_net = Module(new PairedCrossbar(REFILL_CYCLES, relHasData _)(new Release, new ReleaseData))
|
||||
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, rel_net.io.in(id), rel_net.io.out(id), io.release) }
|
||||
|
||||
val probe_net = new BasicCrossbar()(new Probe)
|
||||
val probe_net = Module(new BasicCrossbar()(new Probe))
|
||||
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, probe_net.io.in(id), probe_net.io.out(id), io.probe) }
|
||||
|
||||
val grant_net = new BasicCrossbar()(new Grant)
|
||||
val grant_net = Module(new BasicCrossbar()(new Grant))
|
||||
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, grant_net.io.in(id), grant_net.io.out(id), io.grant) }
|
||||
|
||||
val ack_net = new BasicCrossbar()(new GrantAck)
|
||||
val ack_net = Module(new BasicCrossbar()(new GrantAck))
|
||||
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedFIFOHookup(end, ack_net.io.in(id), ack_net.io.out(id), io.grant_ack) }
|
||||
|
||||
val physicalNetworks = List(acq_net, rel_net, probe_net, grant_net, ack_net)
|
||||
|
||||
2
uncore
2
uncore
@ -1 +1 @@
|
||||
Subproject commit 0f675e35e7503419482b12fb265ef2709a91403a
|
||||
Subproject commit 295a4a5d69987d58de5edea6fad4e750100cffa3
|
||||
Loading…
Reference in New Issue
Block a user