new tilelink arbiter types, reduced release xact trackers
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@ -11,7 +11,7 @@ abstract trait CoherenceConfigConstants {
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trait UncoreConstants {
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val NGLOBAL_ACQ_XACTS = 8
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val NGLOBAL_REL_XACTS = 4
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val NGLOBAL_REL_XACTS = 1
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val MASTER_XACT_ID_MAX_BITS = log2Up(NGLOBAL_ACQ_XACTS+NGLOBAL_REL_XACTS)
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val CACHE_DATA_SIZE_IN_BYTES = 1 << 6
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}
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@ -147,12 +147,24 @@ class TileLinkIO(implicit conf: LogicalNetworkConfiguration) extends UncachedTil
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override def clone = { new TileLinkIO().asInstanceOf[this.type] }
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}
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class UncachedTileLinkIOArbiter(n: Int, co: CoherencePolicy)(implicit conf: LogicalNetworkConfiguration) extends Component {
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/*
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* TODO: Merge the below classes into children of an abstract class in Chisel 2.0
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abstract class UncachedTileLinkIOArbiter(n: Int, co: CoherencePolicy)(implicit conf: LogicalNetworkConfiguration) extends Component {
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def acquireClientXactId(in: Acquire, id: Int): Bits
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def grantClientXactId(in: Grant): Bits
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def arbIdx(in: Grant): UFix
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}
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*/
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class UncachedTileLinkIOArbiterThatAppendsArbiterId(n: Int, co: CoherencePolicy)(implicit conf: LogicalNetworkConfiguration) extends Component {
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def acquireClientXactId(in: Acquire, id: Int) = Cat(in.client_xact_id, UFix(id, log2Up(n)))
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def grantClientXactId(in: Grant) = in.client_xact_id >> UFix(log2Up(n))
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def arbIdx(in: Grant) = in.client_xact_id(log2Up(n)-1,0).toUFix
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val io = new Bundle {
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val in = Vec(n) { new UncachedTileLinkIO }.flip
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val out = new UncachedTileLinkIO
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}
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def acqHasData(acq: LogicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
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val acq_arb = new PairedLockingRRArbiter(n, REFILL_CYCLES, acqHasData _)((new LogicalNetworkIO){new Acquire},(new LogicalNetworkIO){new AcquireData})
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io.out.acquire <> acq_arb.io.out
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@ -160,7 +172,7 @@ class UncachedTileLinkIOArbiter(n: Int, co: CoherencePolicy)(implicit conf: Logi
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arb.data <> req.data
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arb.meta.valid := req.meta.valid
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arb.meta.bits := req.meta.bits
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arb.meta.bits.payload.client_xact_id := Cat(req.meta.bits.payload.client_xact_id, UFix(id, log2Up(n)))
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arb.meta.bits.payload.client_xact_id := acquireClientXactId(req.meta.bits.payload, id)
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req.meta.ready := arb.meta.ready
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}}
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@ -170,13 +182,85 @@ class UncachedTileLinkIOArbiter(n: Int, co: CoherencePolicy)(implicit conf: Logi
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io.out.grant.ready := Bool(false)
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for (i <- 0 until n) {
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val tag = io.out.grant.bits.payload.client_xact_id
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io.in(i).grant.valid := Bool(false)
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when (tag(log2Up(n)-1,0) === UFix(i)) {
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when (arbIdx(io.out.grant.bits.payload) === UFix(i)) {
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io.in(i).grant.valid := io.out.grant.valid
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io.out.grant.ready := io.in(i).grant.ready
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}
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io.in(i).grant.bits := io.out.grant.bits
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io.in(i).grant.bits.payload.client_xact_id := tag >> UFix(log2Up(n))
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io.in(i).grant.bits.payload.client_xact_id := grantClientXactId(io.out.grant.bits.payload)
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}
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}
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class UncachedTileLinkIOArbiterThatPassesId(n: Int, co: CoherencePolicy)(implicit conf: LogicalNetworkConfiguration) extends Component {
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def acquireClientXactId(in: Acquire, id: Int) = in.client_xact_id
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def grantClientXactId(in: Grant) = in.client_xact_id
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def arbIdx(in: Grant): UFix = in.client_xact_id
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val io = new Bundle {
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val in = Vec(n) { new UncachedTileLinkIO }.flip
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val out = new UncachedTileLinkIO
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}
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def acqHasData(acq: LogicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
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val acq_arb = new PairedLockingRRArbiter(n, REFILL_CYCLES, acqHasData _)((new LogicalNetworkIO){new Acquire},(new LogicalNetworkIO){new AcquireData})
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io.out.acquire <> acq_arb.io.out
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io.in.map(_.acquire).zipWithIndex.zip(acq_arb.io.in).map{ case ((req,id), arb) => {
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arb.data <> req.data
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arb.meta.valid := req.meta.valid
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arb.meta.bits := req.meta.bits
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arb.meta.bits.payload.client_xact_id := acquireClientXactId(req.meta.bits.payload, id)
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req.meta.ready := arb.meta.ready
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}}
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val grant_ack_arb = (new RRArbiter(n)){ (new LogicalNetworkIO){new GrantAck} }
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io.out.grant_ack <> grant_ack_arb.io.out
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grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack }
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io.out.grant.ready := Bool(false)
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for (i <- 0 until n) {
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io.in(i).grant.valid := Bool(false)
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when (arbIdx(io.out.grant.bits.payload) === UFix(i)) {
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io.in(i).grant.valid := io.out.grant.valid
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io.out.grant.ready := io.in(i).grant.ready
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}
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io.in(i).grant.bits := io.out.grant.bits
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io.in(i).grant.bits.payload.client_xact_id := grantClientXactId(io.out.grant.bits.payload)
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}
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}
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class UncachedTileLinkIOArbiterThatUsesNewId(n: Int, co: CoherencePolicy)(implicit conf: LogicalNetworkConfiguration) extends Component {
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def acquireClientXactId(in: Acquire, id: Int) = UFix(id, log2Up(n))
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def grantClientXactId(in: Grant) = UFix(0) // DNC
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def arbIdx(in: Grant) = in.client_xact_id
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val io = new Bundle {
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val in = Vec(n) { new UncachedTileLinkIO }.flip
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val out = new UncachedTileLinkIO
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}
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def acqHasData(acq: LogicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
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val acq_arb = new PairedLockingRRArbiter(n, REFILL_CYCLES, acqHasData _)((new LogicalNetworkIO){new Acquire},(new LogicalNetworkIO){new AcquireData})
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io.out.acquire <> acq_arb.io.out
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io.in.map(_.acquire).zipWithIndex.zip(acq_arb.io.in).map{ case ((req,id), arb) => {
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arb.data <> req.data
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arb.meta.valid := req.meta.valid
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arb.meta.bits := req.meta.bits
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arb.meta.bits.payload.client_xact_id := acquireClientXactId(req.meta.bits.payload, id)
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req.meta.ready := arb.meta.ready
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}}
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val grant_ack_arb = (new RRArbiter(n)){ (new LogicalNetworkIO){new GrantAck} }
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io.out.grant_ack <> grant_ack_arb.io.out
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grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack }
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io.out.grant.ready := Bool(false)
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for (i <- 0 until n) {
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io.in(i).grant.valid := Bool(false)
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when (arbIdx(io.out.grant.bits.payload) === UFix(i)) {
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io.in(i).grant.valid := io.out.grant.valid
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io.out.grant.ready := io.in(i).grant.ready
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}
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io.in(i).grant.bits := io.out.grant.bits
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io.in(i).grant.bits.payload.client_xact_id := grantClientXactId(io.out.grant.bits.payload)
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}
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}
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@ -23,7 +23,7 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: UncoreConfiguration) extends
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{
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implicit val lnConf = conf.ln
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val co = conf.co
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require(conf.ln.nClients < NGLOBAL_REL_XACTS) //TODO: handle in config
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//require(conf.ln.nClients < NGLOBAL_REL_XACTS) //TODO: handle in config
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val trackerList = (0 until NGLOBAL_REL_XACTS).map(new VoluntaryReleaseTracker(_, bankId)) ++
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(NGLOBAL_REL_XACTS until NGLOBAL_REL_XACTS + NGLOBAL_ACQ_XACTS).map(new AcquireTracker(_, bankId))
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@ -60,7 +60,7 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: UncoreConfiguration) extends
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val block_releases = Bool(false)
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val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)){Bool()}.lastIndexWhere{b: Bool => b}
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//val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UFix(0)), release.bits.payload.master_xact_id) // TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
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val release_idx = Mux(voluntary, release.meta.bits.header.src, release.meta.bits.payload.master_xact_id)
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val release_idx = Mux(voluntary, UFix(0), release.meta.bits.payload.master_xact_id)
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.client
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t.release.meta.bits := release.meta.bits
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@ -83,7 +83,7 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: UncoreConfiguration) extends
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ack.ready := Bool(true)
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// Create an arbiter for the one memory port
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val outer_arb = new UncachedTileLinkIOArbiter(trackerList.size, conf.co)
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val outer_arb = new UncachedTileLinkIOArbiterThatPassesId(trackerList.size, conf.co)
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outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.master }
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io.master <> outer_arb.io.out
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}
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