riscv/rocket-chip
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  • b4d21148ec get rid of NASTI error assertion Howard Mao 2015-09-22 09:43:42 -0700
  • 64ab45e2e4 add RWX permission bits to address map Howard Mao 2015-09-22 09:43:22 -0700
  • 27745204eb ErrorSlave returns response of correct length for reads Howard Mao 2015-09-22 09:42:57 -0700
  • e72e5a34b5 Fix storage of SP values in DP registers Andrew Waterman 2015-09-21 12:17:46 -0700
  • c6bcc832a1 Chisel3: Don't use Vec.fill for IOs Andrew Waterman 2015-09-20 13:43:39 -0700
  • fd58c52250 Update to latest chisel Andrew Waterman 2015-08-26 22:38:45 -0700
  • 4db6124b2a NASTIErrorSlave should print address Howard Mao 2015-09-18 09:42:41 -0700
  • 8b2341b1b1 use reorder queue instead of extra tag bit to determine TL g_type in NASTI -> TL converter Howard Mao 2015-09-18 09:41:37 -0700
  • 6f85ed191e Add rocketchip_addons to the list of chisel srcs requiring rebuild Colin Schmidt 2015-09-16 12:28:03 -0700
  • 7ecb936bf5 Remove -j from "make run-bmark-tests" in travis +currently causes inconsistency in build success +unclear what root cause is Colin Schmidt 2015-09-16 12:25:00 -0700
  • de81762f7c faster and more conservative float_fix Scott Beamer 2015-09-15 17:19:02 -0700
  • 7e25b1ce03 cleaner/faster comlog without linear search Scott Beamer 2015-09-15 17:18:20 -0700
  • 76bf1da310 [commitlog] zero-extend SP write-back values Christopher Celio 2015-09-15 15:53:36 -0700
  • 3b48d8569c [commitlog] don't print out writebacks to x0 Scott Beamer 2015-09-14 14:32:24 -0700
  • e22bf02a80 [commitlog] CSR's cycle optionally set to instret Christopher Celio 2015-09-11 23:08:23 -0700
  • 7d14abf262 [commitlog] Added privilege-level to output Christopher Celio 2015-09-11 16:08:12 -0700
  • 53a02a62c8 [commitlog] Fix sp/dp bug in FPU writeback Christopher Celio 2015-09-11 15:48:17 -0700
  • d630a03857 [commitlog] Added FP instructions to the commitlog Christopher Celio 2015-09-11 03:45:31 -0700
  • 91458bef1c [commitlog] Initial commit log for integer working Christopher Celio 2015-09-10 18:12:23 -0700
  • 754c47bdd1 Removed "make debug" test from travis Christopher Celio 2015-09-14 15:45:50 -0700
  • d355d81633 regression script bump for new torture that can produce waveforms Colin Schmidt 2015-09-14 13:00:54 -0700
  • bd536d8832 make HTIFModuleIO an anonymous bundle Howard Mao 2015-09-10 17:53:42 -0700
  • 9d89d2a558 get rid of MemIO -> TileLink converters Howard Mao 2015-09-10 17:53:17 -0700
  • f9965648f2 fix up some things in tilelink.scala Howard Mao 2015-09-10 17:53:04 -0700
  • 64717706a9 get rid of non-NASTI RTC module Howard Mao 2015-09-10 17:52:26 -0700
  • 6ee6ea4f1e use Put/Get/PutBlock/GetBlock constructors in broadcast hub Howard Mao 2015-09-10 17:52:12 -0700
  • ae3d96013a make TL -> NASTI converter ingest ClientUncachedTileLinkIO and move functionality to Unwrapper Howard Mao 2015-09-05 21:28:18 -0700
  • 21f96f382c split off SCR functionality from HTIF Howard Mao 2015-09-01 14:47:18 -0700
  • bdc6972a8d separate RTC updates from HTIF Howard Mao 2015-08-12 21:23:17 -0700
  • 24f3fac90a fix broadcast hub and TL -> NASTI converter to support subblock operations Howard Mao 2015-08-10 19:06:02 -0700
  • 3eed7ff238 make float_fix more conservative with replacement Scott Beamer 2015-09-12 11:00:00 -0700
  • a12cd13190 tool to unrecode single floats from commit logs Scott Beamer 2015-09-11 20:19:06 -0700
  • c2344ee2bc Added generated-src-debug to make clean target Christopher Celio 2015-09-11 19:07:33 -0700
  • c9d89226fb Generated *.d file of tests now kept in order Christopher Celio 2015-09-11 18:36:04 -0700
  • c8a7deb950 Added a commitlog post-processor for Rocket Christopher Celio 2015-09-11 16:06:01 -0700
  • 78b2e947de Chisel3 compatibility fixes Andrew Waterman 2015-09-11 15:43:07 -0700
  • 24389a5257 Chisel3 compatibility fixes Andrew Waterman 2015-09-11 15:41:39 -0700
  • 4c3c3c630e add assertions to make sure NASTI -> MemIO converter takes in requests of the right size and len Howard Mao 2015-09-10 17:55:10 -0700
  • 17e971bbfa Add emulator "make debug" and "-j" to travis Christopher Celio 2015-09-10 17:34:16 -0700
  • 6387d31c62 add comments and small fixes for NASTI and SMI Howard Mao 2015-09-10 17:33:48 -0700
  • 8a8d52da4f add convenient constructors for NASTI channels Howard Mao 2015-09-10 17:32:40 -0700
  • d9a2162472 Bump Chisel Christopher Celio 2015-09-10 17:26:41 -0700
  • 8f71c4da2d Reintroduced multiple emulator backend directories Christopher Celio 2015-09-10 17:14:23 -0700
  • 83df4bcc35 Fixed run-bmark-tests make target in vsim Christopher Celio 2015-09-09 22:37:47 -0700
  • af7336ef8b blacklist private branches from travis Colin Schmidt 2015-09-08 15:13:38 -0700
  • d292b6cb13 don't connect rocc-fpu-port without rocc accel Colin Schmidt 2015-09-08 14:42:34 -0700
  • d08b75c472 Merge pull request #15 from ucb-bar/fix_disasm_garbage Andrew Waterman 2015-09-03 17:55:31 -0700
  • 8e9c15c10d If you don't have spike-disasm in your path, your path is dumped to stdout by this line every time you do anything in the entire repo. Ben Keller 2015-09-03 15:36:11 -0700
  • e6b6ff5a1d Update README.md Christopher Celio 2015-09-02 22:55:53 -0700
  • ede1ada053 Add converters and utilities for simpler peripheral interface (SMI) Howard Mao 2015-08-10 19:00:51 -0700
  • 75ec7529af implement NASTI Interconnect generating from configuration address map Howard Mao 2015-08-06 12:48:35 -0700
  • b046c57284 make NASTI -> MemIO converter compliant to AXI4 spec Howard Mao 2015-08-06 12:46:32 -0700
  • 1bfd873888 bump chisel version for seqmem setname Colin Schmidt 2015-08-29 12:53:57 -0700
  • 350d530766 Use Vec.fill, not Vec.apply, for Vec literals Andrew Waterman 2015-08-27 10:00:43 -0700
  • 94287fed90 Avoid type-unsafe assignments Andrew Waterman 2015-08-27 09:57:36 -0700
  • 05d311c517 Use Vec.apply, not Vec.fill, for type nodes Andrew Waterman 2015-08-27 09:47:02 -0700
  • f7d9628de2 Avoid needless use of Vec Andrew Waterman 2015-08-27 09:40:52 -0700
  • 3a1dad7994 Use Vec.apply, not Vec.fill, for type nodes Andrew Waterman 2015-08-27 09:40:24 -0700
  • 0ac6172525 Add "-memsize" flag to emulator Iori YONEJI 2015-02-14 01:56:54 +0900
  • b55765f597 Bump riscv-tools Christopher Celio 2015-08-26 16:08:45 -0700
  • b1e845f370 Add space to README.md Christopher Celio 2015-08-26 14:34:22 -0700
  • b88c283b21 add travis support and tests Scott Beamer 2015-08-25 13:29:20 -0700
  • 333c594d2a respect environment's CXX Scott Beamer 2015-08-25 13:26:14 -0700
  • 49ff021518 bump fpga repo Scott Beamer 2015-08-21 15:39:59 -0700
  • 3d6a060dc3 Bump Scala to 2.11.6 Albert Ou 2015-08-10 23:52:58 -0700
  • bcf95b39e0 bump uncore Henry Cook 2015-08-10 20:08:50 -0700
  • 005752e2a6 use the parameters used to create the original object Henry Cook 2015-08-10 14:35:08 -0700
  • cab12635f8 Merge master into rocc-fpu-port ebb33f2f4b658211960a4c6c023c139420c67212 Colin Schmidt 2015-08-06 08:03:10 -0700
  • 01fc61ba96 Don't construct so many Vecs Andrew Waterman 2015-08-05 18:43:40 -0700
  • a551a12d70 add missing Wire wrap in BasicCrossbar Howard Mao 2015-08-05 17:05:31 -0700
  • a3c9431ee2 bump all submodules for scala version Henry Cook 2015-08-05 16:50:38 -0700
  • eb6583d607 use cloneType in PhysicalNetworkIO Andrew Waterman 2015-08-05 16:47:49 -0700
  • 9b038db34a Upgrade scala to 2.11.6 Andrew Waterman 2015-08-05 15:37:03 -0700
  • 700910adff Chisel3 compatibility fix for <> Andrew Waterman 2015-08-05 15:33:10 -0700
  • 1718333f83 Don't use Vec as lvalue Andrew Waterman 2015-08-05 15:29:33 -0700
  • 546205b174 Chisel3 compatibility: use >>Int instead of >>UInt Andrew Waterman 2015-08-05 15:28:31 -0700
  • 798ddeb5f5 Chisel3 compatibility: use >>Int instead of >>UInt Andrew Waterman 2015-08-04 13:15:17 -0700
  • 2ff2b43c2c Chisel3 compatibility: use >>Int instead of >>UInt Andrew Waterman 2015-08-04 13:13:44 -0700
  • e469785f5e bump scala to 2.11.6 Andrew Waterman 2015-08-03 19:51:17 -0700
  • fb5524372d bump scala to 2.11.6 Andrew Waterman 2015-08-03 19:51:08 -0700
  • fb718f03c1 bump scala to 2.11.6 Andrew Waterman 2015-08-03 19:50:58 -0700
  • d85c46bc60 Chisel3 bulk connect non-commutativity Andrew Waterman 2015-08-03 19:47:16 -0700
  • d4c94c6566 Chisel3 has different Vec semantics Andrew Waterman 2015-08-03 19:08:00 -0700
  • 34b9a7fdc5 Various Chisel3 compatibility changes Andrew Waterman 2015-08-03 18:54:56 -0700
  • 77cf26aeba Chisel3: Flip order of := and <> Andrew Waterman 2015-08-03 18:53:31 -0700
  • c345d72af4 Chisel3: Flip order of := and <> Andrew Waterman 2015-08-03 18:52:59 -0700
  • 121e4fb511 Flip direction of some bulk connects Andrew Waterman 2015-08-03 18:01:14 -0700
  • a21979a2fa Bits -> UInt Andrew Waterman 2015-08-03 18:01:06 -0700
  • ef319edc84 Bits -> UInt Andrew Waterman 2015-08-02 21:03:42 -0700
  • 52fc34a138 Chisel3: bulk connect is not commutative Andrew Waterman 2015-08-01 21:11:25 -0700
  • 9c7a41e8d3 Chisel3: bulk connect is not commutative Andrew Waterman 2015-08-01 21:09:00 -0700
  • 6fc807f069 Chisel3: Avoid subword assignment Andrew Waterman 2015-08-01 21:08:35 -0700
  • 6c0e1e33ab Purge UInt := SInt assignments Andrew Waterman 2015-07-31 15:42:10 -0700
  • 6d7cc37e87 Specify some uninferrable widths Andrew Waterman 2015-07-31 14:23:52 -0700
  • 45cf64dbd7 Use UInt instead of Vec[Bool] Andrew Waterman 2015-07-31 04:59:45 -0700
  • 6d574f8c1b Fix incompatible assignment Andrew Waterman 2015-07-31 00:59:34 -0700
  • 377e17e811 Add Wire() wrap Andrew Waterman 2015-07-31 00:32:02 -0700
  • eb57433f43 Bits -> UInt Andrew Waterman 2015-07-30 23:56:47 -0700
  • 57930e8a26 Chisel3 compatibility potpourri Andrew Waterman 2015-07-30 23:52:42 -0700
  • 0686bdbe28 Avoid cross-module references Andrew Waterman 2015-07-30 23:47:13 -0700