ErrorSlave returns response of correct length for reads
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@ -351,15 +351,32 @@ class NASTIErrorSlave extends NASTIModule {
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when (io.ar.fire()) { printf("Invalid read address %x\n", io.ar.bits.addr) }
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when (io.aw.fire()) { printf("Invalid write address %x\n", io.aw.bits.addr) }
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val r_queue = Module(new Queue(UInt(width = nastiRIdBits), 2))
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r_queue.io.enq.valid := io.ar.valid
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r_queue.io.enq.bits := io.ar.bits.id
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io.ar.ready := r_queue.io.enq.ready
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io.r.valid := r_queue.io.deq.valid
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io.r.bits.id := r_queue.io.deq.bits
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val r_queue = Module(new Queue(new NASTIReadAddressChannel, 2))
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r_queue.io.enq <> io.ar
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val responding = Reg(init = Bool(false))
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val beats_left = Reg(init = UInt(0, nastiXLenBits))
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when (!responding && r_queue.io.deq.valid) {
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responding := Bool(true)
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beats_left := r_queue.io.deq.bits.len
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}
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io.r.valid := r_queue.io.deq.valid && responding
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io.r.bits.id := r_queue.io.deq.bits.id
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io.r.bits.data := UInt(0)
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io.r.bits.resp := Bits("b11")
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io.r.bits.last := Bool(true)
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r_queue.io.deq.ready := io.r.ready
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io.r.bits.last := beats_left === UInt(0)
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r_queue.io.deq.ready := io.r.fire() && io.r.bits.last
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when (io.r.fire()) {
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when (beats_left === UInt(0)) {
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responding := Bool(false)
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} .otherwise {
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beats_left := beats_left - UInt(0)
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}
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}
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val draining = Reg(init = Bool(false))
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io.w.ready := draining
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